VERILOG language

LCD1602\clkdelay.bsf
.......\clkdelay.v
.......\db\LCD_test.db_info
.......\..\LCD_test.sld_design_entry.sci
.......\..\prev_cmp_LCD_test.asm.qmsg
.......\..\prev_cmp_LCD_test.fit.qmsg
.......\..\prev_cmp_LCD_test.map.qmsg
.......\..\prev_cmp_LCD_test.qmsg
.......\..\prev_cmp_LCD_test.tan.qmsg
.......\LCD1602.bsf
.......\LCD1602.v
.......\LCD1602.v.bak
.......\LCD_test.asm.rpt
.......\LCD_test.bdf
.......\LCD_test.cdf
.......\LCD_test.done
.......\LCD_test.fit.rpt
.......\LCD_test.fit.smsg
.......\LCD_test.fit.summary
.......\LCD_test.flow.rpt
.......\LCD_test.map.rpt
.......\LCD_test.map.smsg
.......\LCD_test.map.summary
.......\LCD_test.pin
.......\LCD_test.pof
.......\LCD_test.qpf
.......\LCD_test.qsf
.......\LCD_test.qws
.......\LCD_test.tan.rpt
.......\LCD_test.tan.summary
.......\LCD_test_assignment_defaults.qdf
.......\MAXII240_570T100C5N_PIN.tcl
.......\db
LCD1602

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