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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-03-26
  • Size : 328kb
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  • Author :项****
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Introduction - If you have any usage issues, please Google them yourself
a) sampling rate of about 100KSPS continuous DC voltage for AD conversion, the conversion result of the serial to parallel, Displayed on the digital tube, measuring more than three voltage points, analyze ADC accuracy. b) the input signal is a sinusoidal signal of positive polarity 100Hz, amplitude approximately 4.5V, with the SignalTap II logic analyzer Analyzed the conversion result. c) achieve a single AD conversion: Each time you press the button, and automatically generates a set of CS clock to complete a conversion, the conversion result Results are displayed on digital.
Packet file list
(Preview for download)


AD_4
....\AD_3.asm.rpt
....\AD_3.bdf
....\AD_3.done
....\AD_3.dpf
....\AD_3.fit.rpt
....\AD_3.fit.smsg
....\AD_3.fit.summary
....\AD_3.flow.rpt
....\AD_3.jdi
....\AD_3.map.rpt
....\AD_3.map.summary
....\AD_3.merge.rpt
....\AD_3.pin
....\AD_3.pof
....\AD_3.qpf
....\AD_3.qsf
....\AD_3.qws
....\AD_3.sim.rpt
....\AD_3.sof
....\AD_3.tan.rpt
....\AD_3.tan.summary
....\AD_3.vwf
....\AD_3_assignment_defaults.qdf
....\db
....\..\add_sub_5ch.tdf
....\..\add_sub_lkc.tdf
....\..\add_sub_mkc.tdf
....\..\AD_3.db_info
....\..\AD_3.sim.cvwf
....\..\AD_3.sim_ori.vwf
....\..\AD_3.sld_design_entry.sci
....\..\altsyncram_1ss3.tdf
....\..\altsyncram_3ss3.tdf
....\..\altsyncram_5ss3.tdf
....\..\altsyncram_9ps3.tdf
....\..\altsyncram_bps3.tdf
....\..\altsyncram_dms3.tdf
....\..\altsyncram_dps3.tdf
....\..\altsyncram_ggq1.tdf
....\..\altsyncram_igq1.tdf
....\..\altsyncram_kgq1.tdf
....\..\altsyncram_sdq1.tdf
....\..\alt_u_div_q2f.tdf
....\..\alt_u_div_u2f.tdf
....\..\cmpr_5cc.tdf
....\..\cmpr_6cc.tdf
....\..\cmpr_8cc.tdf
....\..\cmpr_9cc.tdf
....\..\cntr_02j.tdf
....\..\cntr_1ci.tdf
....\..\cntr_45j.tdf
....\..\cntr_7ai.tdf
....\..\cntr_gui.tdf
....\..\cntr_nbi.tdf
....\..\cntr_obi.tdf
....\..\cntr_pbi.tdf
....\..\cntr_sbi.tdf
....\..\cntr_ubi.tdf
....\..\cntr_v1j.tdf
....\..\decode_rqf.tdf
....\..\logic_util_heursitic.dat
....\..\lpm_constant_nf6.tdf
....\..\lpm_constant_uf6.tdf
....\..\lpm_divide_1tp.tdf
....\..\lpm_divide_3tp.tdf
....\..\mux_aoc.tdf
....\..\mux_boc.tdf
....\..\mux_eoc.tdf
....\..\prev_cmp_AD_3.asm.qmsg
....\..\prev_cmp_AD_3.fit.qmsg
....\..\prev_cmp_AD_3.map.qmsg
....\..\prev_cmp_AD_3.merge.qmsg
....\..\prev_cmp_AD_3.qmsg
....\..\prev_cmp_AD_3.sim.qmsg
....\..\prev_cmp_AD_3.tan.qmsg
....\..\sign_div_unsign_slh.tdf
....\..\sign_div_unsign_ulh.tdf
....\..\wed.wsf
....\fp.bsf
....\fp.vhd
....\fp.vhd.bak
....\incremental_db
....\..............\compiled_partitions
....\..............\...................\AD_3.autoh_e4eb58185d954d358c52b26e0df67201.map.dpi
....\..............\...................\AD_3.autoh_e4eb58185d954d358c52b26e0df67201.map.kpt
....\..............\...................\AD_3.autoh_e4eb58185d954d358c52b26e0df67201.map.logdb
....\..............\...................\AD_3.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.dpi
....\..............\...................\AD_3.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.kpt
....\..............\...................\AD_3.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.logdb
....\..............\...................\AD_3.db_info
....\..............\...................\AD_3.root_partition.cmp.dfp
....\..............\...................\AD_3.root_partition.cmp.kpt
....\..............\...................\AD_3.root_partition.cmp.logdb
....\..............\...................\AD_3.root_partition.map.dpi
....\..............\...................\AD_3.root_partition.map.kpt
....\..............\README
....\kzq.bsf
....\kzq.vhd
....\kzq.vhd.bak
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