Altera Corporation introduced the latest development board DE1. The data for the DE1 FPGA code, including the ADC, audio processing, video output, etc., for your use and reference.

FPGA\DE1_SoC_ADC\.qsys_edit\filters.xml
....\...........\..........\preferences.xml
....\...........\c5_pin_model_dump.txt
....\...........\DE1_SoC_ADC.cdf
....\...........\DE1_SoC_ADC.done
....\...........\DE1_SoC_ADC.fit.smsg
....\...........\DE1_SoC_ADC.fit.summary
....\...........\DE1_SoC_ADC.jdi
....\...........\DE1_SoC_ADC.map.smsg
....\...........\DE1_SoC_ADC.map.summary
....\...........\DE1_SoC_ADC.pin
....\...........\DE1_SoC_ADC.qpf
....\...........\DE1_SoC_ADC.qsf
....\...........\DE1_SoC_ADC.qws
....\...........\DE1_SoC_ADC.sdc
....\...........\DE1_SoC_ADC.sof
....\...........\DE1_SoC_ADC.sta.summary
....\...........\DE1_SoC_ADC.v
....\...........\........QSYS\synthesis\DE1_SoC_QSYS.qip
....\...........\............\.........\DE1_SoC_QSYS.v
....\...........\............\.........\submodules\altera_avalon_dc_fifo.v
....\...........\............\.........\..........\altera_avalon_mm_clock_crossing_bridge.v
....\...........\............\.........\..........\altera_avalon_sc_fifo.v
....\...........\............\.........\..........\altera_avalon_st_pipeline_base.v
....\...........\............\.........\..........\altera_avalon_st_pipeline_stage.sv
....\...........\............\.........\..........\altera_dcfifo_synchronizer_bundle.v
....\...........\............\.........\..........\altera_irq_clock_crosser.sv
....\...........\............\.........\..........\altera_merlin_arbitrator.sv
....\...........\............\.........\..........\altera_merlin_burst_uncompressor.sv
....\...........\............\.........\..........\altera_merlin_master_agent.sv
....\...........\............\.........\..........\altera_merlin_master_translator.sv
....\...........\............\.........\..........\altera_merlin_slave_agent.sv
....\...........\............\.........\..........\altera_merlin_slave_translator.sv
....\...........\............\.........\..........\altera_merlin_traffic_limiter.sv
....\...........\............\.........\..........\altera_reset_controller.sdc
....\...........\............\.........\..........\altera_reset_controller.v
....\...........\............\.........\..........\altera_reset_synchronizer.v
....\...........\............\.........\..........\DE1_SoC_QSYS_addr_router.sv
....\...........\............\.........\..........\DE1_SoC_QSYS_addr_router_001.sv
....\...........\............\.........\..........\DE1_SoC_QSYS_addr_router_002.sv
....\...........\............\.........\..........\DE1_SoC_QSYS_altpll_0.qip
....\...........\............\.........\..........\DE1_SoC_QSYS_altpll_0.v
....\...........\............\.........\..........\DE1_SoC_QSYS_cmd_xbar_demux.sv
....\...........\............\.........\..........\DE1_SoC_QSYS_cmd_xbar_demux_001.sv
....\...........\............\.........\..........\DE1_SoC_QSYS_cmd_xbar_demux_002.sv
....\...........\............\.........\..........\DE1_SoC_QSYS_cmd_xbar_mux.sv
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu.ocp
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu.sdc
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu.v
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_bht_ram.mif
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_dc_tag_ram.mif
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_ic_tag_ram.mif
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_jtag_debug_module_sysclk.v
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_jtag_debug_module_tck.v
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_jtag_debug_module_wrapper.v
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_mult_cell.v
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_ociram_default_contents.mif
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_oci_test_bench.v
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_rf_ram_a.mif
....\...........\............\.........\..........\DE1_SoC_QSYS_cpu_rf_ram_b.mif
....\...........\............\.......

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