verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer

vga_pannel_design\src\pll_vga.v
.................\...\pll_vga.v.bak
.................\...\system_ctrl.v
.................\...\system_ctrl.v.bak
.................\...\vga_display.v
.................\...\vga_display.v.bak
.................\...\vga_driver.v
.................\...\vga_driver.v_
.................\...\vga_pannel_design.v
.................\...\vga_pannel_design.v.bak
.................\vga_pannel_design.asm.rpt
.................\vga_pannel_design.done
.................\vga_pannel_design.dpf
.................\vga_pannel_design.fit.rpt
.................\vga_pannel_design.fit.smsg
.................\vga_pannel_design.fit.summary
.................\vga_pannel_design.flow.rpt
.................\vga_pannel_design.map.rpt
.................\vga_pannel_design.map.smsg
.................\vga_pannel_design.map.summary
.................\vga_pannel_design.pin
.................\vga_pannel_design.pof
.................\vga_pannel_design.qpf
.................\vga_pannel_design.qsf
.................\vga_pannel_design.qws
.................\vga_pannel_design.sdc
.................\vga_pannel_design.sof
.................\vga_pannel_design.sta.rpt
.................\vga_pannel_design.sta.summary
.................\vga_pannel_design.tan.rpt
.................\vga_pannel_design.tan.summary
.................\vga_pannel_design.tcl
.................\vga_pannel_design_assignment_defaults.qdf
.................\src
vga_pannel_design

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