Based development board made of taxi meter for college curriculum design

chuzhuche\FPGA_PROJECT1.PRJFPG
.........\FPGA_Project1.PrjFpgStructure
.........\FPGA_Project1.SO
.........\History\History.event
.........\LELEchongzuo.event
.........\ProjectOutputs\$$code$$.vhd
.........\..............\$$temp0.vhd
.........\..............\Default - All Constraints\AND2S.EDN
.........\..............\.........................\CDIV256DC50.EDN
.........\..............\.........................\Default - All Constraints.event
.........\..............\.........................\FPGA_PROJECT1.bfl
.........\..............\.........................\fpga_project1.bgn
.........\..............\.........................\fpga_project1.bit
.........\..............\.........................\fpga_project1.bld
.........\..............\.........................\FPGA_PROJECT1.edf
.........\..............\.........................\FPGA_PROJECT1.FlwCmp
.........\..............\.........................\FPGA_PROJECT1.mof
.........\..............\.........................\FPGA_PROJECT1.mpf
.........\..............\.........................\fpga_project1.ncd
.........\..............\.........................\fpga_project1.ngd
.........\..............\.........................\FPGA_PROJECT1.npl
.........\..............\.........................\fpga_project1.pad
.........\..............\.........................\fpga_project1.par
.........\..............\.........................\fpga_project1.rbt
.........\..............\.........................\fpga_project1.twr
.........\..............\.........................\FPGA_PROJECT1.ucf
.........\..............\.........................\fpga_project1.xpi
.........\..............\.........................\FPGA_PROJECT1_BUILD.UCF
.........\..............\.........................\fpga_project1_cclk.bgn
.........\..............\.........................\fpga_project1_cclk.bit
.........\..............\.........................\fpga_project1_cclk.rbt
.........\..............\.........................\FPGA_PROJECT1_CoreGen.txt
.........\..............\.........................\fpga_project1_map.mrp
.........\..............\.........................\fpga_project1_map.ncd
.........\..............\.........................\fpga_project1_map.ngm
.........\..............\.........................\fpga_project1_map.pcf
.........\..............\.........................\fpga_project1_pad.csv
.........\..............\.........................\fpga_project1_pad.txt
.........\..............\.........................\FPGA_PROJECT1_Synth.log
.........\..............\.........................\IOBUF8B.VHD
.........\..............\.........................\J16B_8B2.VHD
.........\..............\.........................\J8B_8S.VHD
.........\..............\.........................\LCD16X2A.EDN
.........\..............\.........................\Sheet1.VHD
.........\..............\.........................\Status Report.Txt
.........\..............\.........................\_blf\FPGA_PROJECT1_body.blf
.........\..............\.........................\....\FPGA_PROJECT1_header.blf
.........\..............\.........................\....\IOBUF8B_body.blf
.........\..............\.........................\....\IOBUF8B_header.blf
.........\..............\.........................\....\JFQLCD_body.blf
.........\..............\.........................\....\JFQLCD_header.blf
.........\..............\.........................\....\JFQZMK_body.blf
.........\..............\.........................\....\JFQZMK_header.blf
.........\..............\.........................\....\LessThan_32u_32u_body.blf
.........\..............\.........................\....\LessThan_32u_32u_header.blf
.........\..............\.........................\....\_blf.event
.........\..............\.........................\.ngo\AND2S.ngo
.........\..............\.........................\....\CDIV256DC50.ngo
.........\..............\.........................\....\fpga_project1.ngo
.........\..............\.........................\....\LCD16X2A.ngo
.........\..............\.........................\....\netlist.lst
.........\........

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．