It is an UART interface that is written by me in VHDL to receive and send datas from/to FPGA.

uart_tx\uart_tx\db\logic_util_heursitic.dat
.......\.......\..\prev_cmp_uart_tx.qmsg
.......\.......\..\uart_tx.amm.cdb
.......\.......\..\uart_tx.asm.qmsg
.......\.......\..\uart_tx.asm.rdb
.......\.......\..\uart_tx.asm_labs.ddb
.......\.......\..\uart_tx.cbx.xml
.......\.......\..\uart_tx.cmp.bpm
.......\.......\..\uart_tx.cmp.cdb
.......\.......\..\uart_tx.cmp.hdb
.......\.......\..\uart_tx.cmp.kpt
.......\.......\..\uart_tx.cmp.logdb
.......\.......\..\uart_tx.cmp.rdb
.......\.......\..\uart_tx.cmp0.ddb
.......\.......\..\uart_tx.cmp1.ddb
.......\.......\..\uart_tx.cmp2.ddb
.......\.......\..\uart_tx.cmp_merge.kpt
.......\.......\..\uart_tx.db_info
.......\.......\..\uart_tx.fit.qmsg
.......\.......\..\uart_tx.hier_info
.......\.......\..\uart_tx.hif
.......\.......\..\uart_tx.idb.cdb
.......\.......\..\uart_tx.lpc.html
.......\.......\..\uart_tx.lpc.rdb
.......\.......\..\uart_tx.lpc.txt
.......\.......\..\uart_tx.map.bpm
.......\.......\..\uart_tx.map.cdb
.......\.......\..\uart_tx.map.hdb
.......\.......\..\uart_tx.map.kpt
.......\.......\..\uart_tx.map.logdb
.......\.......\..\uart_tx.map.qmsg
.......\.......\..\uart_tx.map_bb.cdb
.......\.......\..\uart_tx.map_bb.hdb
.......\.......\..\uart_tx.map_bb.logdb
.......\.......\..\uart_tx.pre_map.cdb
.......\.......\..\uart_tx.pre_map.hdb
.......\.......\..\uart_tx.rtlv.hdb
.......\.......\..\uart_tx.rtlv_sg.cdb
.......\.......\..\uart_tx.rtlv_sg_swap.cdb
.......\.......\..\uart_tx.sgdiff.cdb
.......\.......\..\uart_tx.sgdiff.hdb
.......\.......\..\uart_tx.sld_design_entry.sci
.......\.......\..\uart_tx.sld_design_entry_dsc.sci
.......\.......\..\uart_tx.smart_action.txt
.......\.......\..\uart_tx.smp_dump.txt
.......\.......\..\uart_tx.sta.qmsg
.......\.......\..\uart_tx.sta.rdb
.......\.......\..\uart_tx.sta_cmp.7_slow.tdb
.......\.......\..\uart_tx.syn_hier_info
.......\.......\..\uart_tx.tis_db_list.ddb
.......\.......\db
.......\.......\incremental_db\compiled_partitions\uart_tx.db_info
.......\.......\..............\...................\uart_tx.root_partition.cmp.cdb
.......\.......\..............\...................\uart_tx.root_partition.cmp.dfp
.......\.......\..............\...................\uart_tx.root_partition.cmp.hdb
.......\.......\..............\...................\uart_tx.root_partition.cmp.kpt
.......\.......\..............\...................\uart_tx.root_partition.cmp.logdb
.......\.......\..............\...................\uart_tx.root_partition.cmp.rcfdb
.......\.......\..............\...................\uart_tx.root_partition.map.cdb
.......\.......\..............\...................\uart_tx.root_partition.map.dpi
.......\.......\..............\...................\uart_tx.root_partition.map.hbdb.cdb
.......\.......\..............\...................\uart_tx.root_partition.map.hbdb.hb_info
.......\.......\..............\...................\uart_tx.root_partition.map.hbdb.hdb
.......\.......\..............\...................\uart_tx.root_partition.map.hbdb.sig
.......\.......\..............\...................\uart_tx.root_partition.map.hdb
.......\.......\..............\...................\uart_tx.root_partition.map.kpt
.......\.......\..............\compiled_partitions
.......\.......\..............\README
.......\.......\incremental_db
.......\.......\uart_tx.asm.rpt
.......\.......\uart_tx.done
.......\.......\uart_tx.fit.rpt
.......\.......\uart_tx.fit.smsg
.......\.......\uart_tx.fit.summary
.......\.......\uart_tx.flow.rpt
.......\.......\uart_tx.map.rpt
.......\.......\uart_tx.map.summary
.......\.......\uart_tx.pin
.......\.......\uart_tx.pof
.......\.......\uart_tx.qpf
.......\.......\uart_tx.qsf
.......\.......\uart_tx.qsf.bak
.......\.......\uart_tx.sof
.......\.......\uart_tx.sta.rpt
.......\.......\uart_tx.sta.summary
.......\.......\uart_tx.vhd
.......\.......\uart_tx.vhd.bak
.......\.......\work\uart_tx\_primary.dat
.......\.......\....\.......\_primary.dbs
.......\.......\....\uart_tx
.......\.......\....\_info
.......\.......\....\_temp
.......\.......\....\_vmake
.......\.......\work
.......\uart_tx
uart_tx

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