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  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-03-18
  • Size : 2.48mb
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  • Author :周****
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Introduction - If you have any usage issues, please Google them yourself
Simple and practical program written in VHDL D flip-flop
Packet file list
(Preview for download)


d_latch
.......\db
.......\..\d_latch.amm.cdb
.......\..\d_latch.asm.qmsg
.......\..\d_latch.asm.rdb
.......\..\d_latch.cbx.xml
.......\..\d_latch.cmp.hdb
.......\..\d_latch.cmp.kpt
.......\..\d_latch.cmp.rdb
.......\..\d_latch.cmp0.ddb
.......\..\d_latch.cmp1.ddb
.......\..\d_latch.cmp2.ddb
.......\..\d_latch.cmp_merge.kpt
.......\..\d_latch.db_info
.......\..\d_latch.eda.qmsg
.......\..\d_latch.fit.qmsg
.......\..\d_latch.hier_info
.......\..\d_latch.hif
.......\..\d_latch.idb.cdb
.......\..\d_latch.lpc.html
.......\..\d_latch.lpc.rdb
.......\..\d_latch.lpc.txt
.......\..\d_latch.map.bpm
.......\..\d_latch.map.cdb
.......\..\d_latch.map.hdb
.......\..\d_latch.map.kpt
.......\..\d_latch.map.logdb
.......\..\d_latch.map.qmsg
.......\..\d_latch.map_bb.cdb
.......\..\d_latch.map_bb.hdb
.......\..\d_latch.map_bb.logdb
.......\..\d_latch.pre_map.cdb
.......\..\d_latch.pre_map.hdb
.......\..\d_latch.root_partition.map.reg_db.cdb
.......\..\d_latch.rpp.qmsg
.......\..\d_latch.rtlv.hdb
.......\..\d_latch.rtlv_sg.cdb
.......\..\d_latch.rtlv_sg_swap.cdb
.......\..\d_latch.sgate.rvd
.......\..\d_latch.sgate_sm.rvd
.......\..\d_latch.sgdiff.cdb
.......\..\d_latch.sgdiff.hdb
.......\..\d_latch.sld_design_entry.sci
.......\..\d_latch.sld_design_entry_dsc.sci
.......\..\d_latch.smart_action.txt
.......\..\d_latch.sta.qmsg
.......\..\d_latch.sta.rdb
.......\..\d_latch.syn_hier_info
.......\..\d_latch.tis_db_list.ddb
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_d_latch.qmsg
.......\d_latch.asm.rpt
.......\d_latch.done
.......\d_latch.eda.rpt
.......\d_latch.fit.rpt
.......\d_latch.fit.smsg
.......\d_latch.fit.summary
.......\d_latch.flow.rpt
.......\d_latch.jdi
.......\d_latch.map.rpt
.......\d_latch.map.summary
.......\d_latch.pin
.......\d_latch.pof
.......\d_latch.qpf
.......\d_latch.qsf
.......\d_latch.sof
.......\d_latch.sta.rpt
.......\d_latch.sta.summary
.......\d_latch.vhd
.......\d_latch_nativelink_simulation.rpt
.......\incremental_db
.......\..............\compiled_partitions
.......\..............\...................\d_latch.db_info
.......\..............\...................\d_latch.root_partition.cmp.cdb
.......\..............\...................\d_latch.root_partition.cmp.dfp
.......\..............\...................\d_latch.root_partition.cmp.hdb
.......\..............\...................\d_latch.root_partition.cmp.kpt
.......\..............\...................\d_latch.root_partition.cmp.logdb
.......\..............\...................\d_latch.root_partition.cmp.rcfdb
.......\..............\...................\d_latch.root_partition.map.cdb
.......\..............\...................\d_latch.root_partition.map.dpi
.......\..............\...................\d_latch.root_partition.map.hbdb.cdb
.......\..............\...................\d_latch.root_partition.map.hbdb.hb_info
.......\..............\...................\d_latch.root_partition.map.hbdb.hdb
.......\..............\...................\d_latch.root_partition.map.hbdb.sig
.......\..............\...................\d_latch.root_partition.map.hdb
.......\..............\...................\d_latch.root_partition.map.kpt
.......\..............\README
.......\quartus_nativelink_synthesis.log
.......\simulation
.......\..........\modelsim
.......\..........\........\d_latch.cr.mti
.......\..........\........\d_latch.mpf
.......\..........\........\d_latch.sft
.......\..........\........\d_latch.vho
.......\..........\........\d_latch.vht
.......\..........\........\d_latch.vht.bak
.......\..........\........\d_latch_fast.vho
.......\..........\........\d_latch_modelsim.xrf
.......\..........\........\d_latch_run_msim_gate_vhdl.do
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