Manchester encoder Verilog and VHDL realization and moore and mealy machines were used to describe it, compare the two implementations of different methods. And in each case are given a test script, I hope useful to you.

t2_manchester_coder\db\logic_util_heursitic.dat
...................\..\man.db_info
...................\..\man.sld_design_entry.sci
...................\..\prev_cmp_man.qmsg
...................\incremental_db\compiled_partitions\man.db_info
...................\..............\...................\man.root_partition.map.dpi
...................\..............\...................\man.root_partition.map.kpt
...................\..............\README
...................\man.bdf
...................\man.done
...................\man.flow.rpt
...................\man.map.rpt
...................\man.map.summary
...................\man.qpf
...................\man.qsf
...................\man.qws
...................\man_assignment_defaults.qdf
...................\man_mealy.bsf
...................\man_mealy.v.bak
...................\man_mealy.vhd
...................\man_mealy.vhd.bak
...................\man_mealy_tb.vhd
...................\man_mealy_tb.vhd.bak
...................\man_mealy_vlg.v
...................\man_mealy_vlg.v.bak
...................\man_mealy_vlg_tb.v
...................\man_mealy_vlg_tb.v.bak
...................\man_moore.bsf
...................\man_moore.vhd
...................\man_moore.vhd.bak
...................\man_moore_tb.vhd
...................\man_moore_tb.vhd.bak
...................\man_nativelink_simulation.rpt
...................\modelsim.ini
...................\simulation\modelsim\man_run_msim_rtl_verilog.do
...................\..........\........\man_run_msim_rtl_verilog.do.bak
...................\..........\........\man_run_msim_rtl_verilog.do.bak1
...................\..........\........\man_run_msim_rtl_verilog.do.bak10
...................\..........\........\man_run_msim_rtl_verilog.do.bak11
...................\..........\........\man_run_msim_rtl_verilog.do.bak2
...................\..........\........\man_run_msim_rtl_verilog.do.bak3
...................\..........\........\man_run_msim_rtl_verilog.do.bak4
...................\..........\........\man_run_msim_rtl_verilog.do.bak5
...................\..........\........\man_run_msim_rtl_verilog.do.bak6
...................\..........\........\man_run_msim_rtl_verilog.do.bak7
...................\..........\........\man_run_msim_rtl_verilog.do.bak8
...................\..........\........\man_run_msim_rtl_verilog.do.bak9
...................\..........\........\man_run_msim_rtl_vhdl.do
...................\..........\........\man_run_msim_rtl_vhdl.do.bak
...................\..........\........\man_run_msim_rtl_vhdl.do.bak1
...................\..........\........\man_run_msim_rtl_vhdl.do.bak2
...................\..........\........\man_run_msim_rtl_vhdl.do.bak3
...................\..........\........\man_run_msim_rtl_vhdl.do.bak4
...................\..........\........\man_run_msim_rtl_vhdl.do.bak5
...................\..........\........\man_run_msim_rtl_vhdl.do.bak6
...................\..........\........\msim_transcript
...................\..........\........\rtl_work\man_mealy\behaviour.dat
...................\..........\........\........\.........\behaviour.dbs
...................\..........\........\........\.........\behaviour.prw
...................\..........\........\........\.........\behaviour.psm
...................\..........\........\........\.........\_primary.dat
...................\..........\........\........\.........\_primary.dbs
...................\..........\........\........\........._tb\behaviour.dat
...................\..........\........\........\............\behaviour.dbs
...................\..........\........\........\............\behaviour.prw
...................\..........\........\........\............\behaviour.psm
...................\..........\........\........\............\_primary.dat
...................\..........\........\........\............\_primary.dbs
...................\..........\........\........\_info
...................\..........\........\........\_vmake
...................\..........\........\vsim.wlf
...................\stg.docx
...................\.imulation\modelsim\rtl_work\man_mealy
...................

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