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t3_sdram

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-03-05
  • Size : 7.09mb
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  • Author :宋****
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Introduction - If you have any usage issues, please Google them yourself
Sdram read and write operations to complete, with a test script file has been verified through simulation. The program includes power-on initialization module, refresh module, reading and writing module, and use FSM controls all modules for reading and writing data.
Packet file list
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t3_sdram\altddio_out0.bsf
........\altddio_out0.cmp
........\altddio_out0.ppf
........\altddio_out0.qip
........\altddio_out0.v
........\altddio_out0_bb.v
........\altddio_sdram_cmd.bsf
........\altddio_sdram_cmd.cmp
........\altddio_sdram_cmd.inc
........\altddio_sdram_cmd.ppf
........\altddio_sdram_cmd.qip
........\altddio_sdram_cmd.v
........\altddio_sdram_cmd_bb.v
........\altddio_sdram_cmd_inst.v
........\altpll0.bsf
........\altpll0.cmp
........\altpll0.ppf
........\altpll0.qip
........\altpll0.v
........\altpll0_bb.v
........\cont_wave.do
........\db\logic_util_heursitic.dat
........\..\prev_cmp_t3.map.qmsg
........\..\prev_cmp_t3.qmsg
........\..\t3.amm.cdb
........\..\t3.asm.qmsg
........\..\t3.asm.rdb
........\..\t3.asm_labs.ddb
........\..\t3.cbx.xml
........\..\t3.cmp.bpm
........\..\t3.cmp.cdb
........\..\t3.cmp.hdb
........\..\t3.cmp.kpt
........\..\t3.cmp.logdb
........\..\t3.cmp.rdb
........\..\t3.cmp_merge.kpt
........\..\t3.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
........\..\t3.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
........\..\t3.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
........\..\t3.db_info
........\..\t3.eda.qmsg
........\..\t3.fit.qmsg
........\..\t3.hier_info
........\..\t3.hif
........\..\t3.idb.cdb
........\..\t3.lpc.html
........\..\t3.lpc.rdb
........\..\t3.lpc.txt
........\..\t3.map.bpm
........\..\t3.map.cdb
........\..\t3.map.hdb
........\..\t3.map.kpt
........\..\t3.map.logdb
........\..\t3.map.qmsg
........\..\t3.map.rdb
........\..\t3.map_bb.cdb
........\..\t3.map_bb.hdb
........\..\t3.map_bb.logdb
........\..\t3.pre_map.cdb
........\..\t3.pre_map.hdb
........\..\t3.root_partition.map.reg_db.cdb
........\..\t3.routing.rdb
........\..\t3.rtlv.hdb
........\..\t3.rtlv_sg.cdb
........\..\t3.rtlv_sg_swap.cdb
........\..\t3.sgdiff.cdb
........\..\t3.sgdiff.hdb
........\..\t3.sld_design_entry.sci
........\..\t3.sld_design_entry_dsc.sci
........\..\t3.smart_action.txt
........\..\t3.smp_dump.txt
........\..\t3.sta.qmsg
........\..\t3.sta.rdb
........\..\t3.sta_cmp.8_slow_1200mv_85c.tdb
........\..\t3.syn_hier_info
........\..\t3.tiscmp.fastest_slow_1200mv_0c.ddb
........\..\t3.tiscmp.fastest_slow_1200mv_85c.ddb
........\..\t3.tiscmp.fast_1200mv_0c.ddb
........\..\t3.tiscmp.slow_1200mv_0c.ddb
........\..\t3.tiscmp.slow_1200mv_85c.ddb
........\..\t3.tis_db_list.ddb
........\..\t3.tmw_info
........\dq_port.bsf
........\dq_port.v
........\dq_port.v.bak
........\e1240.tcl
........\f.do
........\f.do.bak
........\greybox_tmp\cbx_args.txt
........\incremental_db\compiled_partitions\t3.db_info
........\..............\...................\t3.root_partition.cmp.cdb
........\..............\...................\t3.root_partition.cmp.dfp
........\..............\...................\t3.root_partition.cmp.hdb
........\..............\...................\t3.root_partition.cmp.kpt
........\..............\...................\t3.root_partition.cmp.logdb
........\..............\...................\t3.root_partition.cmp.rcfdb
........\..............\...................\t3.root_partition.map.cdb
........\..............\...................\t3.root_partition.map.dpi
........\..............\...................\t3.root_partition.map.hbdb.cdb
........\..............\...................\t3.root_partition.map.hbdb.hb_info
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