Use FPGA ip core to achieve the 256-point FFT conversion with vhdL language.

fft256\ctrl_fft.vhd
......\ctrl_fft.vhd.bak
......\fft256.asm.rpt
......\fft256.done
......\fft256.eda.rpt
......\fft256.fit.rpt
......\fft256.fit.smsg
......\fft256.fit.summary
......\fft256.flow.rpt
......\fft256.jdi
......\fft256.map.rpt
......\fft256.map.summary
......\fft256.merge.rpt
......\fft256.pin
......\fft256.pof
......\fft256.qpf
......\fft256.qsf
......\fft256.qws
......\fft256.sof
......\fft256.tan.rpt
......\fft256.tan.summary
......\fft256.vhd
......\fft256.vhd.bak
......\fft256_nativelink_simulation.rpt
......\fft256_vhd_tst.vhd
......\fft256_vhd_tst.vhd.bak
......\fft_burst.bsf
......\fft_burst.cmp
......\fft_burst.html
......\fft_burst.qip
......\fft_burst.vhd
......\fft_burst.vho
......\fft_burst_1n256cos.hex
......\fft_burst_1n256sin.hex
......\fft_burst_2n256cos.hex
......\fft_burst_2n256sin.hex
......\fft_burst_3n256cos.hex
......\fft_burst_3n256sin.hex
......\fft_burst_gb.v
......\fft_burst_model.m
......\fft_burst_nativelink.tcl
......\fft_burst_tb.m
......\fft_burst_tb.v
......\fft_burst_tb.vhd
......\imag_input.txt
......\real_input.txt
......\stp1.stp
......\velocity.log
fft256

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