Use Verilog language divide by 3, in Quartus debugging through!

clk_div_3\clk_div_3.asm.rpt
.........\clk_div_3.done
.........\clk_div_3.dpf
.........\clk_div_3.eda.rpt
.........\clk_div_3.fit.rpt
.........\clk_div_3.fit.smsg
.........\clk_div_3.fit.summary
.........\clk_div_3.flow.rpt
.........\clk_div_3.jdi
.........\clk_div_3.map.rpt
.........\clk_div_3.map.summary
.........\clk_div_3.merge.rpt
.........\clk_div_3.pin
.........\clk_div_3.pof
.........\clk_div_3.qpf
.........\clk_div_3.qsf
.........\clk_div_3.qws
.........\clk_div_3.sim.rpt
.........\clk_div_3.sof
.........\clk_div_3.tan.rpt
.........\clk_div_3.tan.summary
.........\clk_div_3.v
.........\clk_div_3.v.bak
.........\clk_div_3.vwf
.........\clk_div_3_assignment_defaults.qdf
.........\db\altsyncram_k1p3.tdf
.........\..\altsyncram_lms3.tdf
.........\..\altsyncram_m1p3.tdf
.........\..\clk_div_3.asm.qmsg
.........\..\clk_div_3.asm_labs.ddb
.........\..\clk_div_3.cbx.xml
.........\..\clk_div_3.cmp.bpm
.........\..\clk_div_3.cmp.cdb
.........\..\clk_div_3.cmp.ecobp
.........\..\clk_div_3.cmp.hdb
.........\..\clk_div_3.cmp.kpt
.........\..\clk_div_3.cmp.logdb
.........\..\clk_div_3.cmp.rdb
.........\..\clk_div_3.cmp.tdb
.........\..\clk_div_3.cmp0.ddb
.........\..\clk_div_3.cmp_merge.kpt
.........\..\clk_div_3.db_info
.........\..\clk_div_3.eco.cdb
.........\..\clk_div_3.eda.qmsg
.........\..\clk_div_3.eds_overflow
.........\..\clk_div_3.fit.qmsg
.........\..\clk_div_3.fnsim.cdb
.........\..\clk_div_3.fnsim.hdb
.........\..\clk_div_3.fnsim.qmsg
.........\..\clk_div_3.hier_info
.........\..\clk_div_3.hif
.........\..\clk_div_3.lpc.html
.........\..\clk_div_3.lpc.rdb
.........\..\clk_div_3.lpc.txt
.........\..\clk_div_3.map.bpm
.........\..\clk_div_3.map.cdb
.........\..\clk_div_3.map.ecobp
.........\..\clk_div_3.map.hdb
.........\..\clk_div_3.map.kpt
.........\..\clk_div_3.map.logdb
.........\..\clk_div_3.map.qmsg
.........\..\clk_div_3.map_bb.cdb
.........\..\clk_div_3.map_bb.hdb
.........\..\clk_div_3.map_bb.logdb
.........\..\clk_div_3.pre_map.cdb
.........\..\clk_div_3.pre_map.hdb
.........\..\clk_div_3.rpp.qmsg
.........\..\clk_div_3.rtlv.hdb
.........\..\clk_div_3.rtlv_sg.cdb
.........\..\clk_div_3.rtlv_sg_swap.cdb
.........\..\clk_div_3.sgate.rvd
.........\..\clk_div_3.sgate_sm.rvd
.........\..\clk_div_3.sgdiff.cdb
.........\..\clk_div_3.sgdiff.hdb
.........\..\clk_div_3.sim.cvwf
.........\..\clk_div_3.sim.hdb
.........\..\clk_div_3.sim.qmsg
.........\..\clk_div_3.sim.rdb
.........\..\clk_div_3.simfam
.........\..\clk_div_3.sld_design_entry.sci
.........\..\clk_div_3.sld_design_entry_dsc.sci
.........\..\clk_div_3.syn_hier_info
.........\..\clk_div_3.tan.qmsg
.........\..\clk_div_3.tis_db_list.ddb
.........\..\clk_div_3_global_asgn_op.abo
.........\..\cmpr_5cc.tdf
.........\..\cmpr_7cc.tdf
.........\..\cmpr_8cc.tdf
.........\..\cntr_02j.tdf
.........\..\cntr_aai.tdf
.........\..\cntr_bai.tdf
.........\..\cntr_cai.tdf
.........\..\cntr_gui.tdf
.........\..\cntr_sbi.tdf
.........\..\decode_rqf.tdf
.........\..\mux_aoc.tdf
.........\..\mux_aqc.tdf
.........\..\mux_ooc.tdf
.........\..\prev_cmp_clk_div_3.asm.qmsg
.........\..\prev_cmp_clk_div_3.eda.qmsg

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．