In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.

fir_test01\CycloneII_Pin.tcl
..........\db\add_sub_gvd.tdf
..........\..\altsyncram_2981.tdf
..........\..\altsyncram_9g31.tdf
..........\..\altsyncram_bg31.tdf
..........\..\altsyncram_e681.tdf
..........\..\altsyncram_e981.tdf
..........\..\altsyncram_kc81.tdf
..........\..\altsyncram_m981.tdf
..........\..\altsyncram_ng31.tdf
..........\..\cmpr_6cc.tdf
..........\..\cmpr_7cc.tdf
..........\..\cmpr_8cc.tdf
..........\..\cmpr_9cc.tdf
..........\..\cmpr_mag.tdf
..........\..\cntr_bmf.tdf
..........\..\cntr_g6f.tdf
..........\..\cntr_ikf.tdf
..........\..\cntr_kkf.tdf
..........\..\cntr_okf.tdf
..........\..\cntr_skf.tdf
..........\..\fir_test01.db_info
..........\..\fir_test01.sld_design_entry.sci
..........\..\logic_util_heursitic.dat
..........\..\mux_8oc.tdf
..........\..\mux_boc.tdf
..........\..\prev_cmp_fir_test01.qmsg
..........\..\shift_taps_3jm.tdf
..........\..\shift_taps_4jm.tdf
..........\..\shift_taps_5jm.tdf
..........\..\shift_taps_7jm.tdf
..........\..\shift_taps_ajm.tdf
..........\..\shift_taps_hkm.tdf
..........\..\shift_taps_okm.tdf
..........\..\shift_taps_phm.tdf
..........\fir.bsf
..........\fir.html
..........\fir.qip
..........\fir.v
..........\fir.vec
..........\fir.vo
..........\fir_ast.vhd
..........\fir_bb.v
..........\fir_coef_int.txt
..........\......mpiler-library\accum.v
..........\....................\addr_cnt_dn.v
..........\....................\addr_cnt_dn_poly.v
..........\....................\addr_cnt_up.v
..........\....................\at_sink_mod.v
..........\....................\at_sink_mod_bin.v
..........\....................\at_sink_mod_par.v
..........\....................\at_src_mod.v
..........\....................\at_src_mod_par.v
..........\....................\auk_dspip_avalon_streaming_block_sink_fftfprvs_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_block_sink_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_block_source_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_controller_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_controller_pe_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_monitor_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_sink_fir_130.ocp
..........\....................\auk_dspip_avalon_streaming_sink_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_sink_model_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_source_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_source_from_monitor_fir_130.vhd
..........\....................\auk_dspip_avalon_streaming_source_model_fir_130.vhd
..........\....................\auk_dspip_delay_fir_130.vhd
..........\....................\auk_dspip_fastaddsub_fir_130.vhd
..........\....................\auk_dspip_fastadd_fir_130.vhd
..........\....................\auk_dspip_fast_accumulator_fir_130.vhd
..........\....................\auk_dspip_fifo_pfc_fir_130.vhd
..........\....................\auk_dspip_fir_accumulator_fir_130.vhd
..........\....................\auk_dspip_fir_adders_fir_130.vhd
..........\....................\auk_dspip_fir_adder_tree_fir_130.vhd
..........\....................\auk_dspip_fir_avalon_slave_write_fir_130.vhd
..........\....................\auk_dspip_fir_coef_banks_fixed_fir_130.vhd
..........\....................\auk_dspip_fir_data_memory_bank_fir_130.vhd
..........\....................\auk_dspip_fir_dspblock_bank_fir_130.vhd
..........\....................\auk_dspip_fir_dspblock_cascade_bank_fir_130.vhd
..........\....................\auk_dspip_fir_lib_pkg_fir_130.vhd
..........\....................\auk_dspip_fir_math_pkg_fir_130.vhd
..........\....................\auk_dspip_fir_memory_simple_dual_fir_130.vhd
..........\....................\auk_dspip_fir_memory_single_fir_130.vhd
..........\....................\auk_dspip_fir_memory_true_dual_fir_130.vhd
..........\....................\auk_dspip_fir_mult_bank_fir_130.vhd
..........\....................\auk_dspip_fir_top_dec_half_sym_fir

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