Examples of VHDL prepared by the detection of a button, using the image stabilization, each key is pressed, the output pulse of a button.

key\db\key.asm.qmsg
...\..\key.asm.rdb
...\..\key.asm_labs.ddb
...\..\key.cbx.xml
...\..\key.cmp.cdb
...\..\key.cmp.hdb
...\..\key.cmp.idb
...\..\key.cmp.kpt
...\..\key.cmp.logdb
...\..\key.cmp.rdb
...\..\key.cmp0.ddb
...\..\key.db_info
...\..\key.eda.qmsg
...\..\key.fit.qmsg
...\..\key.hier_info
...\..\key.hif
...\..\key.ipinfo
...\..\key.lpc.html
...\..\key.lpc.rdb
...\..\key.lpc.txt
...\..\key.map.cdb
...\..\key.map.hdb
...\..\key.map.logdb
...\..\key.map.qmsg
...\..\key.map.rdb
...\..\key.pplq.rdb
...\..\key.pre_map.hdb
...\..\key.pti_db_list.ddb
...\..\key.root_partition.map.reg_db.cdb
...\..\key.routing.rdb
...\..\key.rpp.qmsg
...\..\key.rtlv.hdb
...\..\key.rtlv_sg.cdb
...\..\key.rtlv_sg_swap.cdb
...\..\key.sgate.rvd
...\..\key.sgate_sm.rvd
...\..\key.sgdiff.cdb
...\..\key.sgdiff.hdb
...\..\key.sld_design_entry.sci
...\..\key.sld_design_entry_dsc.sci
...\..\key.smart_action.txt
...\..\key.sta.qmsg
...\..\key.sta.rdb
...\..\key.sta_cmp.5_slow.tdb
...\..\key.syn_hier_info
...\..\key.tis_db_list.ddb
...\..\key.vpr.ammdb
...\..\logic_util_heursitic.dat
...\..\prev_cmp_key.qmsg
...\incremental_db\compiled_partitions\key.db_info
...\..............\...................\key.root_partition.map.kpt
...\..............\README
...\key.qpf
...\key.qsf
...\key.qws
...\KEY.vhd
...\KEY.vhd.bak
...\key_nativelink_simulation.rpt
...\output_files\key.asm.rpt
...\............\key.cdf
...\............\key.done
...\............\key.eda.rpt
...\............\key.fit.rpt
...\............\key.fit.smsg
...\............\key.fit.summary
...\............\key.flow.rpt
...\............\key.jdi
...\............\key.map.rpt
...\............\key.map.summary
...\............\key.pin
...\............\key.pof
...\............\key.sta.rpt
...\............\key.sta.summary
...\simulation\modelsim\key.sft
...\..........\........\key.vho
...\..........\........\KEY.vht
...\..........\........\KEY.vht.bak
...\..........\........\key_modelsim.xrf
...\..........\........\key_run_msim_rtl_vhdl.do
...\..........\........\key_run_msim_rtl_vhdl.do.bak
...\..........\........\key_run_msim_rtl_vhdl.do.bak1
...\..........\........\key_run_msim_rtl_vhdl.do.bak2
...\..........\........\key_vhd.sdo
...\..........\........\modelsim.ini
...\..........\........\msim_transcript
...\..........\........\rtl_work\key\rtl.dat
...\..........\........\........\...\rtl.dbs
...\..........\........\........\...\rtl.prw
...\..........\........\........\...\rtl.psm
...\..........\........\........\...\_primary.dat
...\..........\........\........\...\_primary.dbs
...\..........\........\........\..._vhd_tst\key_arch.dat
...\..........\........\........\...........\key_arch.dbs
...\..........\........\........\...........\key_arch.prw
...\..........\........\........\...........\key_arch.psm
...\..........\........\........\...........\_primary.dat
...\..........\........\........\...........\_primary.dbs
...\..........\........\........\_info
...\..........\........\........\_vmake
...\..........\........\vsim.wlf

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