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Syn_FIFO(wanzheng)

  • Category : VHDL-FPGA-Verilog
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  • Update : 2014-01-23
  • Size : 426kb
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Introduction - If you have any usage issues, please Google them yourself
Based IPcore synchronous FIFO preparation. Read and write data width are 8bit, a depth of 32.
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Syn_FIFO(wanzheng)
..................\flag_gen.v
..................\fuse.log
..................\fuse.xmsgs
..................\fuseRelaunch.cmd
..................\ipcore_dir
..................\..........\coregen.cgp
..................\..........\coregen.log
..................\..........\create_RAM.tcl
..................\..........\RAM
..................\..........\RAM.asy
..................\..........\RAM.gise
..................\..........\RAM.ncf
..................\..........\RAM.ngc
..................\..........\RAM.sym
..................\..........\RAM.v
..................\..........\RAM.veo
..................\..........\RAM.xco
..................\..........\RAM.xise
..................\..........\...\blk_mem_gen_v7_3_readme.txt
..................\..........\...\doc
..................\..........\...\...\blk_mem_gen_v7_3_vinfo.html
..................\..........\...\...\pg058-blk-mem-gen.pdf
..................\..........\...\example_design
..................\..........\...\..............\RAM_exdes.ucf
..................\..........\...\..............\RAM_exdes.vhd
..................\..........\...\..............\RAM_exdes.xdc
..................\..........\...\..............\RAM_prod.vhd
..................\..........\...\implement
..................\..........\...\.........\implement.bat
..................\..........\...\.........\implement.sh
..................\..........\...\.........\planAhead_ise.bat
..................\..........\...\.........\planAhead_ise.sh
..................\..........\...\.........\planAhead_ise.tcl
..................\..........\...\.........\xst.prj
..................\..........\...\.........\xst.scr
..................\..........\...\simulation
..................\..........\...\..........\addr_gen.vhd
..................\..........\...\..........\bmg_stim_gen.vhd
..................\..........\...\..........\bmg_tb_pkg.vhd
..................\..........\...\..........\checker.vhd
..................\..........\...\..........\data_gen.vhd
..................\..........\...\..........\functional
..................\..........\...\..........\..........\simcmds.tcl
..................\..........\...\..........\..........\simulate_isim.bat
..................\..........\...\..........\..........\simulate_mti.bat
..................\..........\...\..........\..........\simulate_mti.do
..................\..........\...\..........\..........\simulate_mti.sh
..................\..........\...\..........\..........\simulate_ncsim.sh
..................\..........\...\..........\..........\simulate_vcs.sh
..................\..........\...\..........\..........\ucli_commands.key
..................\..........\...\..........\..........\vcs_session.tcl
..................\..........\...\..........\..........\wave_mti.do
..................\..........\...\..........\..........\wave_ncsim.sv
..................\..........\...\..........\RAM_synth.vhd
..................\..........\...\..........\RAM_tb.vhd
..................\..........\...\..........\random.vhd
..................\..........\...\..........\timing
..................\..........\...\..........\......\simcmds.tcl
..................\..........\...\..........\......\simulate_isim.bat
..................\..........\...\..........\......\simulate_mti.bat
..................\..........\...\..........\......\simulate_mti.do
..................\..........\...\..........\......\simulate_mti.sh
..................\..........\...\..........\......\simulate_ncsim.sh
..................\..........\...\..........\......\simulate_vcs.sh
..................\..........\...\..........\......\ucli_commands.key
..................\..........\...\..........\......\vcs_session.tcl
..................\..........\...\..........\......\wave_mti.do
..................\..........\...\..........\......\wave_ncsim.sv
..................\..........\RAM_flist.txt
..................\..........\RAM_xmdf.tcl
..................\..........\summary.log
..................\..........\tmp
..................\..........\...\RAM.lso
..................\..........\...\_cg
..................\..........\...\_xmsgs
...
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