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electronic_clock

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-12-14
  • Size : 1.28mb
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Introduction - If you have any usage issues, please Google them yourself
An electronic clock that can display hours, minutes, seconds.And the user can set the time.What s more,it can achieve stopwatch function, alarm function, adjust brightness LED tube.
Packet file list
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electronic_clock
................\db
................\..\add_sub_3dc.tdf
................\..\add_sub_4dc.tdf
................\..\add_sub_59c.tdf
................\..\add_sub_5dc.tdf
................\..\add_sub_6dc.tdf
................\..\add_sub_7dc.tdf
................\..\add_sub_89c.tdf
................\..\add_sub_8dc.tdf
................\..\add_sub_9dc.tdf
................\..\alt_u_div_4oe.tdf
................\..\alt_u_div_aoe.tdf
................\..\lpm_divide_e5m.tdf
................\..\lpm_divide_ktl.tdf
................\..\pao_xian.asm.qmsg
................\..\pao_xian.cbx.xml
................\..\pao_xian.cmp.bpm
................\..\pao_xian.cmp.cdb
................\..\pao_xian.cmp.ecobp
................\..\pao_xian.cmp.hdb
................\..\pao_xian.cmp.logdb
................\..\pao_xian.cmp.rdb
................\..\pao_xian.cmp.tdb
................\..\pao_xian.cmp0.ddb
................\..\pao_xian.cmp_bb.cdb
................\..\pao_xian.cmp_bb.hdb
................\..\pao_xian.cmp_bb.logdb
................\..\pao_xian.cmp_bb.rcf
................\..\pao_xian.db_info
................\..\pao_xian.dbp
................\..\pao_xian.eco.cdb
................\..\pao_xian.fit.qmsg
................\..\pao_xian.hier_info
................\..\pao_xian.hif
................\..\pao_xian.map.bpm
................\..\pao_xian.map.cdb
................\..\pao_xian.map.ecobp
................\..\pao_xian.map.hdb
................\..\pao_xian.map.logdb
................\..\pao_xian.map.qmsg
................\..\pao_xian.map_bb.cdb
................\..\pao_xian.map_bb.hdb
................\..\pao_xian.map_bb.logdb
................\..\pao_xian.merge.qmsg
................\..\pao_xian.pre_map.cdb
................\..\pao_xian.pre_map.hdb
................\..\pao_xian.psp
................\..\pao_xian.pss
................\..\pao_xian.rtlv.hdb
................\..\pao_xian.rtlv_sg.cdb
................\..\pao_xian.rtlv_sg_swap.cdb
................\..\pao_xian.sgdiff.cdb
................\..\pao_xian.sgdiff.hdb
................\..\pao_xian.signalprobe.cdb
................\..\pao_xian.sld_design_entry.sci
................\..\pao_xian.sld_design_entry_dsc.sci
................\..\pao_xian.syn_hier_info
................\..\pao_xian.tan.qmsg
................\..\sign_div_unsign_akh.tdf
................\..\sign_div_unsign_dkh.tdf
................\fenpin.vhd
................\miaobiao.vhd
................\moshi.vhd
................\mux3_1.vhd
................\naozhongset.vhd
................\naozhongspeaker.vhd
................\pao_xian.asm.rpt
................\pao_xian.cdf
................\pao_xian.done
................\pao_xian.dpf
................\pao_xian.fit.rpt
................\pao_xian.fit.smsg
................\pao_xian.fit.summary
................\pao_xian.flow.rpt
................\pao_xian.map.rpt
................\pao_xian.map.summary
................\pao_xian.merge.rpt
................\pao_xian.pin
................\pao_xian.pof
................\pao_xian.qpf
................\pao_xian.qsf
................\pao_xian.qws
................\pao_xian.sof
................\pao_xian.tan.rpt
................\pao_xian.tan.summary
................\pao_xian.vhd
................\paobiao.vhd
................\settime.vhd
................\xianshi.vhd
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