FPGA internal RAM and latches integrated module design, welcome to verify

Latch_sram\latch_sram.qpf
..........\latch_sram.qsf
..........\latch_sram.bdf
..........\latch.bsf
..........\latch_sram.done
..........\latch_test.vhd.bak
..........\latch_test.vhd
..........\latch_test.bsf
..........\kram.bsf
..........\latch_sram.map.summary
..........\SRAM_256Kb.tdf
..........\latch_sram.pin
..........\latch_sram.fit.smsg
..........\latch_sram.fit.summary
..........\SRAM_256Kb.inc
..........\SRAM_256Kb.cmp
..........\SRAM_256Kb.bsf
..........\my_latch.tdf
..........\my_latch.inc
..........\my_latch.cmp
..........\my_latch.bsf
..........\latch_sram.vwf
..........\latch_test.vwf
..........\kram.vwf
..........\kram.vhd.bak
..........\kram.vhd
..........\SRAM_256Kb_waveforms.html
..........\SRAM_256Kb_wave0.jpg
..........\SRAM_256Kb_wave1.jpg
..........\db\latch_sram.db_info
..........\..\latch_sram.map.qmsg
..........\..\latch_sram.sim.qmsg
..........\..\prev_cmp_latch_sram.qmsg
..........\..\latch_sram.sim.cvwf
..........\..\latch_sram.sim.rdb
..........\..\prev_cmp_latch_sram.map.qmsg
..........\..\prev_cmp_latch_sram.fit.qmsg
..........\..\prev_cmp_latch_sram.asm.qmsg
..........\..\prev_cmp_latch_sram.sta.qmsg
..........\..\prev_cmp_latch_sram.eda.qmsg
..........\..\latch_sram.sim.hdb
..........\..\prev_cmp_latch_sram.sim.qmsg
..........\..\latch_sram.fnsim.qmsg
..........\..\latch_sram.fit.qmsg
..........\..\latch_sram.rtlv_sg_swap.cdb
..........\..\latch_sram.map_bb.logdb
..........\..\latch_sram.cmp.cdb
..........\..\latch_sram.asm.qmsg
..........\..\latch_sram.pre_map.hdb
..........\..\latch_sram.cbx.xml
..........\..\latch_sram.hif
..........\..\altsyncram_34t1.tdf
..........\..\latch_sram.rtlv_sg.cdb
..........\..\latch_sram.sta.qmsg
..........\..\latch_sram.hier_info
..........\..\latch_sram.rtlv.hdb
..........\..\latch_sram.cmp.logdb
..........\..\altsyncram_oqt1.tdf
..........\..\latch_sram.psp
..........\..\latch_sram.dbp
..........\..\latch_sram.pss
..........\..\altsyncram_7lq1.tdf
..........\..\latch_sram.eco.cdb
..........\..\latch_sram.syn_hier_info
..........\..\latch_sram.map.ecobp
..........\..\latch_sram.pre_map.cdb
..........\..\latch_sram.eda.qmsg
..........\..\latch_sram.sgdiff.cdb
..........\..\latch_sram.cmp.ecobp
..........\..\latch_sram.cmp_bb.logdb
..........\..\latch_sram.tiscmp.slow_1200mv_85c.ddb
..........\..\latch_sram.sgdiff.hdb
..........\..\latch_sram.sta.rdb
..........\..\latch_sram.cmp.bpm
..........\..\latch_sram.map_bb.cdb
..........\..\latch_sram.map_bb.hdb
..........\..\latch_sram.cmp_bb.rcf
..........\..\latch_sram.eds_overflow
..........\..\wed.wsf
..........\..\latch_sram.map.logdb
..........\..\latch_sram.map.cdb
..........\..\latch_sram.map.hdb
..........\..\latch_sram.map.bpm
..........\..\latch_sram.asm_labs.ddb
..........\..\latch_sram.cmp.rdb
..........\..\latch_sram.tiscmp.fastest_slow_1200mv_85c.ddb
..........\..\latch_sram.cmp_bb.hdb
..........\..\latch_sram.cuda_io_sim_cache.ss_85.hsd
..........\..\latch_sram.cuda_io_sim_cache.tt_85.hsd
..........\..\latch_sram.tis_db_list.ddb
..........\..\altsyncram_ebe1.tdf
..........\..\decode_ira.tdf
..........\..\decode_b7a.tdf
..........\..\mux_2mb.tdf
..........\..\latch_sram.fnsim.cdb
..........\..\latch_sram.cmp_bb.cdb
..........\..\latch_sram.signalprobe.cdb
..........\..\latch_sram.tiscmp.slow_1200mv_0c.ddb
..........\..\latch_sram.tiscmp.fast_1200mv_0c.ddb
..........\..\latch_sram.cmp.hdb

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