The example SPI testbench code of the VMM1.2

spi\tags\asyst_2\rtl\verilog\spi_clgen.v
...\....\.......\...\.......\spi_defines.v
...\....\.......\...\.......\spi_shift.v
...\....\.......\...\.......\spi_top.v
...\....\.......\...\.......\timescale.v
...\....\......3\rtl\verilog\spi_clgen.v
...\....\.......\...\.......\spi_defines.v
...\....\.......\...\.......\spi_shift.v
...\....\.......\...\.......\spi_top.v
...\....\.......\...\.......\timescale.v
...\....\initial\bench\verilog\spi_slave_model.v
...\....\.......\.....\.......\tb_spi_top.v
...\....\.......\.....\.......\wb_master_model.v
...\....\.......\doc\src\spi.doc
...\....\.......\rtl\verilog\spi_clgen.v
...\....\.......\...\.......\spi_defines.v
...\....\.......\...\.......\spi_shift.v
...\....\.......\...\.......\spi_top.v
...\....\.......\...\.......\timescale.v
...\....\.......\sim\run\sim
...\....\.......\...\...\tcl.scr
...\....\rel_1\bench\verilog\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc\spi.pdf
...\....\.....\...\.rc\spi.doc
...\....\.....\rtl\verilog\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim\run\sim
...\....\.....\...\...\tcl.scr
...\....\....2\bench\verilog\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc\spi.pdf
...\....\.....\...\.rc\spi.doc
...\....\.....\rtl\verilog\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim\run\sim
...\....\.....\...\...\tcl.scr
...\....\....3\bench\verilog\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc\spi.pdf
...\....\.....\...\.rc\spi.doc
...\....\.....\rtl\verilog\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim\run\sim
...\....\.....\...\...\tcl.scr
...\....\....4\bench\verilog\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc\spi.pdf
...\....\.....\...\.rc\spi.doc
...\....\.....\rtl\verilog\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim\run\sim
...\....\.....\...\...\tcl.scr
...\....\....5\bench\verilog\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc\spi.pdf
...\....\.....\...\.rc\spi.doc
...\....\.....\rtl\verilog\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim\run\sim
...\....\.....\...\...\tcl.scr
...\....\....6\bench\verilog\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc\spi.pdf
...\....\.....\...\.rc\spi.doc
...\....\.....\rtl\verilog\spi_clgen.v
...\....\.....\...\.......\spi_defines.v
...\....\.....\...\.......\spi_shift.v
...\....\.....\...\.......\spi_top.v
...\....\.....\...\.......\timescale.v
...\....\.....\sim\run\sim
...\....\.....\...\...\tcl.scr
...\....\....7\bench\verilog\spi_slave_model.v
...\....\.....\.....\.......\tb_spi_top.v
...\....\.....\.....\.......\wb_master_model.v
...\....\.....\doc\spi.pdf
...\....\.....\...\.rc\spi.doc
...\....\.....\rtl\verilog\spi_clgen.v
...\....\.....\...\.......\spi_defines.v

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