This a BCD in vhdl programming code in order to be able to make it more intuitive performance out of our way to let it finally 7seg represented more intuitive presentation of the results

jk_TB.v
JK_FF_TB.v
JK_FF.v
DType_PositiveEdgeTriggered_FlipFlop_TB.v
DType_PositiveEdgeTriggered_FlipFlop.v
jk.v
BCDto7Seg.v
BinaryToBCD_4bit (1).v
BinaryToBCD_4bit.v
BinaryToSevenSeg (1).v
BinaryToSevenSeg.v
Counter.v
Counter_TB.v
BCDto7Seg (1).v

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