This the most simple of a binary frequency divider, the fpga is a short code, written in verilog

fenpin
......\db
......\..\FPQ.amm.cdb
......\..\FPQ.asm.qmsg
......\..\FPQ.asm.rdb
......\..\FPQ.asm_labs.ddb
......\..\FPQ.cbx.xml
......\..\FPQ.cmp.bpm
......\..\FPQ.cmp.cdb
......\..\FPQ.cmp.hdb
......\..\FPQ.cmp.kpt
......\..\FPQ.cmp.logdb
......\..\FPQ.cmp.rdb
......\..\FPQ.cmp0.ddb
......\..\FPQ.cmp1.ddb
......\..\FPQ.cmp2.ddb
......\..\FPQ.cmp_merge.kpt
......\..\FPQ.db_info
......\..\FPQ.eda.qmsg
......\..\FPQ.fit.qmsg
......\..\FPQ.hier_info
......\..\FPQ.hif
......\..\FPQ.idb.cdb
......\..\FPQ.lpc.html
......\..\FPQ.lpc.rdb
......\..\FPQ.lpc.txt
......\..\FPQ.map.bpm
......\..\FPQ.map.cdb
......\..\FPQ.map.hdb
......\..\FPQ.map.kpt
......\..\FPQ.map.logdb
......\..\FPQ.map.qmsg
......\..\FPQ.map_bb.cdb
......\..\FPQ.map_bb.hdb
......\..\FPQ.map_bb.logdb
......\..\FPQ.pre_map.cdb
......\..\FPQ.pre_map.hdb
......\..\FPQ.rtlv.hdb
......\..\FPQ.rtlv_sg.cdb
......\..\FPQ.rtlv_sg_swap.cdb
......\..\FPQ.sgdiff.cdb
......\..\FPQ.sgdiff.hdb
......\..\FPQ.sld_design_entry.sci
......\..\FPQ.sld_design_entry_dsc.sci
......\..\FPQ.smart_action.txt
......\..\FPQ.sta.qmsg
......\..\FPQ.sta.rdb
......\..\FPQ.sta_cmp.8_slow.tdb
......\..\FPQ.syn_hier_info
......\..\FPQ.tis_db_list.ddb
......\..\logic_util_heursitic.dat
......\..\prev_cmp_FPQ.qmsg
......\FPQ.asm.rpt
......\FPQ.done
......\FPQ.eda.rpt
......\FPQ.fit.rpt
......\FPQ.fit.smsg
......\FPQ.fit.summary
......\FPQ.flow.rpt
......\FPQ.map.rpt
......\FPQ.map.summary
......\FPQ.pin
......\FPQ.pof
......\FPQ.qpf
......\FPQ.qsf
......\FPQ.sof
......\FPQ.sta.rpt
......\FPQ.sta.summary
......\FPQ.v
......\FPQ.v.bak
......\FPQ_nativelink_simulation.rpt
......\incremental_db
......\..............\compiled_partitions
......\..............\...................\FPQ.db_info
......\..............\...................\FPQ.root_partition.cmp.cbp
......\..............\...................\FPQ.root_partition.cmp.cdb
......\..............\...................\FPQ.root_partition.cmp.dfp
......\..............\...................\FPQ.root_partition.cmp.hdb
......\..............\...................\FPQ.root_partition.cmp.kpt
......\..............\...................\FPQ.root_partition.cmp.logdb
......\..............\...................\FPQ.root_partition.cmp.rcfdb
......\..............\...................\FPQ.root_partition.cmp.re.rcfdb
......\..............\...................\FPQ.root_partition.map.cbp
......\..............\...................\FPQ.root_partition.map.cdb
......\..............\...................\FPQ.root_partition.map.dpi
......\..............\...................\FPQ.root_partition.map.hdb
......\..............\...................\FPQ.root_partition.map.kpt
......\..............\README
......\simulation
......\..........\modelsim
......\..........\........\FPQ.sft
......\..........\........\FPQ.vo
......\..........\........\FPQ_fast.vo
......\..........\........\FPQ_modelsim.xrf
......\..........\........\FPQ_run_msim_rtl_verilog.do
......\..........\........\FPQ_run_msim_rtl_verilog.do.bak
......\..........\........\FPQ_run_msim_rtl_verilog.do.bak1
......\..........\........\FPQ_run_msim_rtl_verilog.do.bak2
......\..........\........\FPQ_run_msim_rtl_verilog.do.bak3
......\..........\........\FPQ_run_msim_rtl_verilog.do.bak4

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