Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners

FPGA2-DSP2 EDMA\db\F2D_EDMA_Top.db_info
...............\..\F2D_EDMA_Top.eco.cdb
...............\..\F2D_EDMA_Top.sld_design_entry.sci
...............\dsp_fifo.qip
...............\F2D_EDMA.qpf
...............\F2D_EDMA.qws
...............\F2D_EDMA_Top.asm.rpt
...............\F2D_EDMA_Top.done
...............\F2D_EDMA_Top.dpf
...............\F2D_EDMA_Top.fit.rpt
...............\F2D_EDMA_Top.fit.smsg
...............\F2D_EDMA_Top.fit.summary
...............\F2D_EDMA_Top.flow.rpt
...............\F2D_EDMA_Top.jdi
...............\F2D_EDMA_Top.map.rpt
...............\F2D_EDMA_Top.map.smsg
...............\F2D_EDMA_Top.map.summary
...............\F2D_EDMA_Top.merge.rpt
...............\F2D_EDMA_Top.pin
...............\F2D_EDMA_Top.qsf
...............\F2D_EDMA_Top.sof
...............\F2D_EDMA_Top.sta.rpt
...............\F2D_EDMA_Top.sta.summary
...............\F2D_EDMA_Top.tan.rpt
...............\F2D_EDMA_Top.tan.summary
...............\F2D_EDMA_Top_assignment_defaults.qdf
...............\ip\dsp_fifo.bsf
...............\..\dsp_fifo.qip
...............\..\dsp_fifo.v
...............\..\dsp_fifo_bb.v
...............\src\dsp_io.v
...............\...\dsp_io.v.bak
...............\...\F2D_EDMA_Top.v
...............\...\F2D_EDMA_Top.v.bak
...............\...\Work_led.v
...............\...\write_sdram.v
...............\...\write_sdram.v.bak
...............\stp1.stp
...............\db
...............\ip
...............\src
FPGA2-DSP2 EDMA

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