Design a 32-bit pipelined MIPS microprocessor, the specific requirements are as follows: 1. At least run the following MIPS32 instruction. ① arithmetic instructions: ADD, ADDU, SUB, SUBU, ADDI, ADDIU. ② logical operation instructions: AND, OR, NOR, XOR, ANDI, ORI, XORI, SLT, SLTU, SLTI, SLTIU. ③ shift instruction: SLL, SLLV, SRL, SRLV, SRA. ④ conditional branch instruction: BEQ, BNE, BGEZ, BGTZ, BLEZ, BLTZ. ⑤ unconditional jump instruction: J, JR. ⑥ data transfer instruction: LW, SW. ⑦ dummy: NOP. (2) using five pipeline technology, adventure on the forwarding or blocking of data functions. 3 In the XUP Virtex-II Pro development system to achieve MIPS microprocessors, requires the CPU to run faster than 25MHz.

ALU.v
DataRAM.v
Decode.v
EX.v
ID.v
IF.v
InstructionROM.v
MipsPipelineCPU.v
MultiRegisters.v
addr_forward_4.v
addr_sel_4.v
con_addr_32.v
ff_lib.v
mux_4.v

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