ALTERA MAX Series FPGA-based development board serial signal generator source. Should be universal. Design environment QUARTUS II. Archive contains the entire project.

XUELIEXINHAOFASHENGQI\db\prev_cmp_XULIEXINHAOFASHENGQI.asm.qmsg
.....................\..\prev_cmp_XULIEXINHAOFASHENGQI.fit.qmsg
.....................\..\prev_cmp_XULIEXINHAOFASHENGQI.map.qmsg
.....................\..\prev_cmp_XULIEXINHAOFASHENGQI.qmsg
.....................\..\prev_cmp_XULIEXINHAOFASHENGQI.sim.qmsg
.....................\..\prev_cmp_XULIEXINHAOFASHENGQI.tan.qmsg
.....................\..\wed.wsf
.....................\..\XULIEXINHAOFASHENGQI.asm.qmsg
.....................\..\XULIEXINHAOFASHENGQI.cbx.xml
.....................\..\XULIEXINHAOFASHENGQI.cmp.cdb
.....................\..\XULIEXINHAOFASHENGQI.cmp.hdb
.....................\..\XULIEXINHAOFASHENGQI.cmp.logdb
.....................\..\XULIEXINHAOFASHENGQI.cmp.rdb
.....................\..\XULIEXINHAOFASHENGQI.cmp.tdb
.....................\..\XULIEXINHAOFASHENGQI.cmp0.ddb
.....................\..\XULIEXINHAOFASHENGQI.db_info
.....................\..\XULIEXINHAOFASHENGQI.eco.cdb
.....................\..\XULIEXINHAOFASHENGQI.eds_overflow
.....................\..\XULIEXINHAOFASHENGQI.fit.qmsg
.....................\..\XULIEXINHAOFASHENGQI.hier_info
.....................\..\XULIEXINHAOFASHENGQI.hif
.....................\..\XULIEXINHAOFASHENGQI.lpc.html
.....................\..\XULIEXINHAOFASHENGQI.lpc.rdb
.....................\..\XULIEXINHAOFASHENGQI.lpc.txt
.....................\..\XULIEXINHAOFASHENGQI.map.cdb
.....................\..\XULIEXINHAOFASHENGQI.map.hdb
.....................\..\XULIEXINHAOFASHENGQI.map.logdb
.....................\..\XULIEXINHAOFASHENGQI.map.qmsg
.....................\..\XULIEXINHAOFASHENGQI.pre_map.cdb
.....................\..\XULIEXINHAOFASHENGQI.pre_map.hdb
.....................\..\XULIEXINHAOFASHENGQI.rtlv.hdb
.....................\..\XULIEXINHAOFASHENGQI.rtlv_sg.cdb
.....................\..\XULIEXINHAOFASHENGQI.rtlv_sg_swap.cdb
.....................\..\XULIEXINHAOFASHENGQI.sgdiff.cdb
.....................\..\XULIEXINHAOFASHENGQI.sgdiff.hdb
.....................\..\XULIEXINHAOFASHENGQI.sim.cvwf
.....................\..\XULIEXINHAOFASHENGQI.sim.hdb
.....................\..\XULIEXINHAOFASHENGQI.sim.qmsg
.....................\..\XULIEXINHAOFASHENGQI.sim.rdb
.....................\..\XULIEXINHAOFASHENGQI.sld_design_entry.sci
.....................\..\XULIEXINHAOFASHENGQI.sld_design_entry_dsc.sci
.....................\..\XULIEXINHAOFASHENGQI.syn_hier_info
.....................\..\XULIEXINHAOFASHENGQI.tan.qmsg
.....................\..\XULIEXINHAOFASHENGQI.tis_db_list.ddb
.....................\..\XULIEXINHAOFASHENGQI.tmw_info
.....................\incremental_db\compiled_partitions\XULIEXINHAOFASHENGQI.root_partition.map.kpt
.....................\..............\README
.....................\XULIEXINHAOFASHENGQI.asm.rpt
.....................\XULIEXINHAOFASHENGQI.cdf
.....................\XULIEXINHAOFASHENGQI.done
.....................\XULIEXINHAOFASHENGQI.dpf
.....................\XULIEXINHAOFASHENGQI.fit.rpt
.....................\XULIEXINHAOFASHENGQI.fit.summary
.....................\XULIEXINHAOFASHENGQI.flow.rpt
.....................\XULIEXINHAOFASHENGQI.map.rpt
.....................\XULIEXINHAOFASHENGQI.map.summary
.....................\XULIEXINHAOFASHENGQI.pin
.....................\XULIEXINHAOFASHENGQI.pof
.....................\XULIEXINHAOFASHENGQI.qpf
.....................\XULIEXINHAOFASHENGQI.qsf
.....................\XULIEXINHAOFASHENGQI.qws
.....................\XULIEXINHAOFASHENGQI.sim.rpt
.....................\XULIEXINHAOFASHENGQI.tan.rpt
.....................\XULIEXINHAOFASHENGQI.tan.summary
.....................\XULIEXINHAOFASHENGQI.vhd
.....................\XULIEXINHAOFASHENGQI.vhd.bak
.....................\XULIEXINHAOFASHENGQI.vwf
.....................\XULIEXINHAOFASHENGQI_assignment_defaults.qdf
.....................\incremental_db\compiled_partitions
.....................\db
.....................\incremental_db
XUELIEXINHAOFASHENGQI

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