2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.

RANGEN
......\DOC
......\...\设计方案说明.docx
......\RANGEN.asm.rpt
......\RANGEN.bsf
......\RANGEN.done
......\RANGEN.fit.rpt
......\RANGEN.fit.smsg
......\RANGEN.fit.summary
......\RANGEN.flow.rpt
......\RANGEN.jdi
......\RANGEN.map.rpt
......\RANGEN.map.summary
......\RANGEN.pin
......\RANGEN.qpf
......\RANGEN.qsf
......\RANGEN.sof
......\RANGEN.sta.rpt
......\RANGEN.sta.summary
......\RANGEN_stp.stp
......\RTL
......\...\RANGEN.v
......\...\RANGEN.v.bak
......\...\clock_div.v
......\...\clock_div.v.bak
......\...\sigxnor.v
......\...\sigxnor.v.bak
......\...\synclk_buf.v
......\...\synclk_buf.v.bak
......\clock_div.bsf
......\sigxnor.bsf
......\synclk_buf.bsf
......\top_Block.bdf

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