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8-way-Responder

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2013-10-05
  • Size : 73kb
  • Downloaded :1次
  • Author :祖****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
8-way Responder proteus Description: 1, the Responder, the reset time, the display timing bit 0 seconds. 2, to be the host announced the question and then press the button to start the timer, then wait eight players answer: If anyone answer, then The display shows the player number, allowed to answer questions and countdown 20S, 20S limit the examination time if nobody answer, then re-start the timer, then need to press the start button again host 3, before that, If the host has not yet announced the start, if anyone answer, then announced the foul, and shows the corresponding player numbers, given the appropriate punishment
Packet file list
(Preview for download)


8路抢答keil
...........\MAIN.ASM
...........\MAIN.LST
...........\MAIN.OBJ
...........\QDQ
...........\QDQ.hex
...........\QDQ.lnp
...........\QDQ.M51
...........\QDQ.Opt
...........\QDQ.plg
...........\QDQ.Uv2
...........\QDQ_Opt.Bak
...........\QDQ_Uv2.Bak
...........\STARTUP.A51
...........\STARTUP.LST
...........\STARTUP.OBJ
8路抢答proteus
..............\Last Loaded Last Loaded QDQ.DBK
..............\Last Loaded Last Loaded QDQ.PWI
..............\Last Loaded QDQ.DBK
..............\Last Loaded QDQ.PWI
..............\QDQ.DSN
..............\QDQ.PWI
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