Altera StratixII FPGA and DSP TS201 implement the bus communication procedures, Verilog realization

fpga_ver\altpll_bus.cmp
........\altpll_bus.inc
........\altpll_bus.ppf
........\altpll_bus.qip
........\altpll_bus.v
........\altpll_bus.v.bak
........\altpll_bus_bb.v
........\altpll_bus_inst.v
........\altpll_bus_wave0.jpg
........\altpll_bus_waveforms.html
........\clear_jitter.v
........\clear_jitter.v.bak
........\db\altsyncram_16p3.tdf
........\..\altsyncram_5q61.tdf
........\..\altsyncram_73p3.tdf
........\..\altsyncram_7ou.tdf
........\..\altsyncram_93p3.tdf
........\..\altsyncram_d3p3.tdf
........\..\altsyncram_dn71.tdf
........\..\altsyncram_h3p3.tdf
........\..\altsyncram_hk71.tdf
........\..\alt_synch_pipe_8u7.tdf
........\..\alt_synch_pipe_9u7.tdf
........\..\alt_synch_pipe_jcb.tdf
........\..\alt_synch_pipe_kcb.tdf
........\..\alt_synch_pipe_nc8.tdf
........\..\alt_synch_pipe_oc8.tdf
........\..\a_graycounter_62c.tdf
........\..\a_graycounter_72c.tdf
........\..\a_graycounter_8gc.tdf
........\..\a_graycounter_9gc.tdf
........\..\a_graycounter_i96.tdf
........\..\cmpr_7dc.tdf
........\..\cmpr_bdc.tdf
........\..\cmpr_ddc.tdf
........\..\cmpr_edc.tdf
........\..\cmpr_v26.tdf
........\..\cntr_06j.tdf
........\..\cntr_4di.tdf
........\..\cntr_5di.tdf
........\..\cntr_7di.tdf
........\..\cntr_9di.tdf
........\..\cntr_iei.tdf
........\..\cntr_ivi.tdf
........\..\cntr_uci.tdf
........\..\dcfifo_bvd1.tdf
........\..\dcfifo_phg1.tdf
........\..\dcfifo_q0i1.tdf
........\..\decode_trf.tdf
........\..\dffpipe_2v8.tdf
........\..\dffpipe_3v8.tdf
........\..\dffpipe_c2e.tdf
........\..\dffpipe_hd9.tdf
........\..\dffpipe_id9.tdf
........\..\dffpipe_jd9.tdf
........\..\dffpipe_kd9.tdf
........\..\dffpipe_ngh.tdf
........\..\fpga_bus_dsp.analyze_file.qmsg
........\..\fpga_bus_dsp.asm.qmsg
........\..\fpga_bus_dsp.asm_labs.ddb
........\..\fpga_bus_dsp.cbx.xml
........\..\fpga_bus_dsp.cmp.bpm
........\..\fpga_bus_dsp.cmp.cdb
........\..\fpga_bus_dsp.cmp.ecobp
........\..\fpga_bus_dsp.cmp.hdb
........\..\fpga_bus_dsp.cmp.kpt
........\..\fpga_bus_dsp.cmp.logdb
........\..\fpga_bus_dsp.cmp.qrpt
........\..\fpga_bus_dsp.cmp.rdb
........\..\fpga_bus_dsp.cmp.tdb
........\..\fpga_bus_dsp.cmp0.ddb
........\..\fpga_bus_dsp.cmp_merge.kpt
........\..\fpga_bus_dsp.db_info
........\..\fpga_bus_dsp.eco.cdb
........\..\fpga_bus_dsp.fit.qmsg
........\..\fpga_bus_dsp.hier_info
........\..\fpga_bus_dsp.hif
........\..\fpga_bus_dsp.lpc.html
........\..\fpga_bus_dsp.lpc.rdb
........\..\fpga_bus_dsp.lpc.txt
........\..\fpga_bus_dsp.map.bpm
........\..\fpga_bus_dsp.map.cdb
........\..\fpga_bus_dsp.map.ecobp
........\..\fpga_bus_dsp.map.hdb
........\..\fpga_bus_dsp.map.kpt
........\..\fpga_bus_dsp.map.logdb
........\..\fpga_bus_dsp.map.qmsg
........\..\fpga_bus_dsp.map_bb.cdb
........\..\fpga_bus_dsp.map_bb.hdb
........\..\fpga_bus_dsp.map_bb.logdb
........\..\fpga_bus_dsp.pre_map.cdb
........\..\fpga_bus_dsp.pre_map.hdb
........\..\fpga_bus_dsp.rpp.qmsg
........\..\fpga_bus_dsp.rtlv.hdb
........\..\fpga_bus_dsp.rtlv_sg.cdb
........\..\fpga_bus_dsp.rtlv_sg_swap.cdb
........\..\fpga_bus_dsp.sgate.rvd
........\..\fpga_bus_dsp.sgate_sm.rvd
........\..\fpga_bus_dsp.sgdiff.cdb
........\..\fpga_bus_dsp.sgdiff.hdb

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