Altera Stratix II FPGA and TS201 DSP through a chain junction communication procedures

fpga2dsp\altddio_in0.bsf
........\altddio_in0.cmp
........\altddio_in0.inc
........\altddio_in0.ppf
........\altddio_in0.qip
........\altddio_in0.v
........\altddio_in0_bb.v
........\altddio_in0_inst.v
........\altlvds_rx0.bsf
........\altlvds_rx0.cmp
........\altlvds_rx0.inc
........\altlvds_rx0.ppf
........\altlvds_rx0.qip
........\altlvds_rx0.v
........\altlvds_rx0_bb.v
........\altlvds_rx0_inst.v
........\altlvds_rx1.bsf
........\altlvds_rx1.cmp
........\altlvds_rx1.inc
........\altlvds_rx1.ppf
........\altlvds_rx1.qip
........\altlvds_rx1.v
........\altlvds_rx1_bb.v
........\altlvds_rx1_inst.v
........\altpll0.bsf
........\altpll0.cmp
........\altpll0.inc
........\altpll0.ppf
........\altpll0.qip
........\altpll0.v
........\altpll0_bb.v
........\altpll0_inst.v
........\altpll0_wave0.jpg
........\altpll0_waveforms.html
........\db\altpll_2g92.tdf
........\..\altpll_5g92.tdf
........\..\altpll_7g92.tdf
........\..\altpll_8h92.tdf
........\..\altsyncram_5bp3.tdf
........\..\altsyncram_og31.tdf
........\..\altsyncram_pap3.tdf
........\..\altsyncram_qap3.tdf
........\..\alt_synch_pipe_gc8.tdf
........\..\alt_synch_pipe_v78.tdf
........\..\a_graycounter_9ic.tdf
........\..\a_graycounter_e47.tdf
........\..\cmpr_efc.tdf
........\..\cmpr_ifc.tdf
........\..\cmpr_jfc.tdf
........\..\cmpr_u46.tdf
........\..\cmpr_v46.tdf
........\..\cntr_7fi.tdf
........\..\cntr_8fi.tdf
........\..\cntr_9fi.tdf
........\..\cntr_d8j.tdf
........\..\cntr_efi.tdf
........\..\cntr_n9j.tdf
........\..\cntr_p1j.tdf
........\..\cntr_t2e.tdf
........\..\dcfifo_oig1.tdf
........\..\ddio_in_l3e.tdf
........\..\decode_4uf.tdf
........\..\dffpipe_ad9.tdf
........\..\dsp2fpga.asm.qmsg
........\..\dsp2fpga.asm_labs.ddb
........\..\dsp2fpga.cbx.xml
........\..\dsp2fpga.cmp.bpm
........\..\dsp2fpga.cmp.cdb
........\..\dsp2fpga.cmp.ecobp
........\..\dsp2fpga.cmp.hdb
........\..\dsp2fpga.cmp.kpt
........\..\dsp2fpga.cmp.logdb
........\..\dsp2fpga.cmp.rdb
........\..\dsp2fpga.cmp_merge.kpt
........\..\dsp2fpga.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
........\..\dsp2fpga.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
........\..\dsp2fpga.db_info
........\..\dsp2fpga.eco.cdb
........\..\dsp2fpga.eds_overflow
........\..\dsp2fpga.fit.qmsg
........\..\dsp2fpga.fnsim.hdb
........\..\dsp2fpga.fnsim.qmsg
........\..\dsp2fpga.hier_info
........\..\dsp2fpga.hif
........\..\dsp2fpga.lpc.html
........\..\dsp2fpga.lpc.rdb
........\..\dsp2fpga.lpc.txt
........\..\dsp2fpga.map.bpm
........\..\dsp2fpga.map.cdb
........\..\dsp2fpga.map.ecobp
........\..\dsp2fpga.map.hdb
........\..\dsp2fpga.map.kpt
........\..\dsp2fpga.map.logdb
........\..\dsp2fpga.map.qmsg
........\..\dsp2fpga.map_bb.cdb
........\..\dsp2fpga.map_bb.hdb
........\..\dsp2fpga.map_bb.logdb
........\..\dsp2fpga.pre_map.cdb
........\..\dsp2fpga.pre_map.hdb
........\..\dsp2fpga.rpp.qmsg

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