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verilog_prj_seq

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-09-23
  • Size : 1.57mb
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  • Author :Red_*****
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Sequence detector, detection sequence "11010", verilog HDL code.
Packet file list
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verilog_prj_seq\db\prev_cmp_verilog_prj_seq.asm.qmsg
...............\..\prev_cmp_verilog_prj_seq.eda.qmsg
...............\..\prev_cmp_verilog_prj_seq.fit.qmsg
...............\..\prev_cmp_verilog_prj_seq.map.qmsg
...............\..\prev_cmp_verilog_prj_seq.qmsg
...............\..\prev_cmp_verilog_prj_seq.tan.qmsg
...............\..\verilog_prj_seq.asm.qmsg
...............\..\verilog_prj_seq.asm_labs.ddb
...............\..\verilog_prj_seq.cbx.xml
...............\..\verilog_prj_seq.cmp.cdb
...............\..\verilog_prj_seq.cmp.hdb
...............\..\verilog_prj_seq.cmp.kpt
...............\..\verilog_prj_seq.cmp.logdb
...............\..\verilog_prj_seq.cmp.rdb
...............\..\verilog_prj_seq.cmp.tdb
...............\..\verilog_prj_seq.cmp0.ddb
...............\..\verilog_prj_seq.db_info
...............\..\verilog_prj_seq.eco.cdb
...............\..\verilog_prj_seq.eda.qmsg
...............\..\verilog_prj_seq.fit.qmsg
...............\..\verilog_prj_seq.hier_info
...............\..\verilog_prj_seq.hif
...............\..\verilog_prj_seq.lpc.html
...............\..\verilog_prj_seq.lpc.rdb
...............\..\verilog_prj_seq.lpc.txt
...............\..\verilog_prj_seq.map.cdb
...............\..\verilog_prj_seq.map.hdb
...............\..\verilog_prj_seq.map.logdb
...............\..\verilog_prj_seq.map.qmsg
...............\..\verilog_prj_seq.pre_map.cdb
...............\..\verilog_prj_seq.pre_map.hdb
...............\..\verilog_prj_seq.rtlv.hdb
...............\..\verilog_prj_seq.rtlv_sg.cdb
...............\..\verilog_prj_seq.rtlv_sg_swap.cdb
...............\..\verilog_prj_seq.sgdiff.cdb
...............\..\verilog_prj_seq.sgdiff.hdb
...............\..\verilog_prj_seq.sld_design_entry.sci
...............\..\verilog_prj_seq.sld_design_entry_dsc.sci
...............\..\verilog_prj_seq.smp_dump.txt
...............\..\verilog_prj_seq.syn_hier_info
...............\..\verilog_prj_seq.tan.qmsg
...............\..\verilog_prj_seq.tis_db_list.ddb
...............\..\verilog_prj_seq.tmw_info
...............\incremental_db\compiled_partitions\verilog_prj_seq.root_partition.map.kpt
...............\..............\README
...............\simulation\modelsim\modelsim.ini
...............\..........\........\msim_transcript
...............\..........\........\rtl_work\@_opt\vopt0jfc6w
...............\..........\........\........\.....\vopt1nkfzt
...............\..........\........\........\.....\vopt43596w
...............\..........\........\........\.....\vopt46aczt
...............\..........\........\........\.....\vopt7jt66w
...............\..........\........\........\.....\vopt8nz8zt
...............\..........\........\........\.....\voptb3g36w
...............\..........\........\........\.....\voptc5j84w
...............\..........\........\........\.....\voptf59zzt
...............\..........\........\........\.....\voptfm854w
...............\..........\........\........\.....\voptiiss6w
...............\..........\........\........\.....\voptimywzt
...............\..........\........\........\.....\voptj5y14w
...............\..........\........\........\.....\voptm2fn6w
...............\..........\........\........\.....\voptnmrsfs
...............\..........\........\........\.....\vopts2mjnn
...............\..........\........\........\.....\voptx3cimn
...............\..........\........\........\.....\voptxiagnn
...............\..........\........\........\.....\_deps
...............\..........\........\........\verilog_prj_seq\_primary.dat
...............\..........\........\........\...............\_primary.dbs
...............\..........\........\........\...............\_primary.vhd
...............\..........\........\........\..............._test\_primary.dat
...............\..........\........\........\....................\_primary.dbs
...............\..........\........\........\....................\_primary.vhd
...............\..........\........\........\_info
...............\..........\........\........\_vmake
...............\..........\........\verilog_libs\altera_mf_ver\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\_primary.dat
............
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