DDS signal generator generates a variety of waveforms including sine, triangle wave, square wave, sawtooth wave. Running on Altera Cyclone FPGA platform.

xinhaoyuan\a1.bsf
..........\a1.inc
..........\a1.ppf
..........\a1.vhd
..........\a1_wave0.jpg
..........\a1_waveforms.html
..........\add1.vhd
..........\ADDER16B.vhd
..........\ADDER22B.vhd
..........\adder8B.vhd
..........\boxing_rom.bsf
..........\boxing_rom.vhd
..........\cnt10.vhd
..........\cnt10ge.vhd
..........\cnt16_xiangwei.vhd
..........\cnt5_boxing.vhd
..........\cnt_125.bsf
..........\cnt_125.vhd
..........\cnt_16xiangwei.vhd
..........\cnt_5.bsf
..........\cnt_5.vhd
..........\cnt_5boxing.vhd
..........\cnt_8.vhd
..........\data\boxing.mif
..........\....\dcrs.mif
..........\....\delta.mif
..........\....\icrs.mif
..........\....\sin.mif
..........\....\square.mif
..........\data
..........\.b\altsyncram_f7k2.tdf
..........\..\altsyncram_hc61.tdf
..........\..\altsyncram_pc61.tdf
..........\..\altsyncram_v7k2.tdf
..........\..\decode_ogi.tdf
..........\..\xinhaoyuan.db_info
..........\db
..........\DDSP.bdf
..........\DDSP.bsf
..........\div5.bsf
..........\div5.vhd
..........\greybox_tmp\cbx_args.txt
..........\greybox_tmp
..........\interface.bdf
..........\interface.bsf
..........\jsq16.vhd
..........\jsq5.vhd
..........\mcs51.bsf
..........\mcs51.vhd
..........\mutlq.vhd
..........\qd.bsf
..........\qd.vhd
..........\REG22B.vhd
..........\REG8B.vhd
..........\xinghaoyuan.bdf
..........\xinhaoyuan.asm.rpt
..........\xinhaoyuan.done
..........\xinhaoyuan.dpf
..........\xinhaoyuan.fit.rpt
..........\xinhaoyuan.fit.smsg
..........\xinhaoyuan.fit.summary
..........\xinhaoyuan.flow.rpt
..........\xinhaoyuan.map.rpt
..........\xinhaoyuan.map.summary
..........\xinhaoyuan.pin
..........\xinhaoyuan.pof
..........\xinhaoyuan.qpf
..........\xinhaoyuan.qsf
..........\xinhaoyuan.sof
..........\xinhaoyuan.tan.rpt
..........\xinhaoyuan.tan.summary
..........\xinhaoyuan_assignment_defaults.qdf
..........\z1.bdf
xinhaoyuan

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