i2c ip core support slave and master mode

i2c_core\chips\i2c_core\i2c_core.cst
........\.....\........\i2c_core.rpt
........\.....\........\i2c_core.ws
........\.....\........-optimized\i2c_core-optimized.cst
........\.....\..................\i2c_core-optimized.rpt
........\.....\..................\i2c_core-optimized.ws
........\files\L0.rpt
........\.....\L1.rpt
........\.....\L2.rpt
........\i2c_core.exp
........\workdirs\unisim\Anal.info
........\........\......\Anal.out
........\........\......\VCOMPONENTS.sim
........\........\......\VCOMPONENTS.syn
........\........\Virtex2_macro\Anal.info
........\........\.............\Anal.out
........\........\.............\COMPONENTS.sim
........\........\.............\COMPONENTS.syn
........\........\WORK\Anal.info
........\........\....\Anal.out
........\........\....\i2c_core.hnl
........\........\....\I2C_CORE.mra
........\........\....\i2c_core.out
........\........\....\I2C_CORE.sim
........\........\....\i2c_core.sts
........\........\....\I2C_CORE.syn
........\........\....\I2C_CORE__STRUCTURAL.sim
........\........\....\I2C_CORE__STRUCTURAL.syn
........\........\....\SIMPLE_I2C.mra
........\........\....\SIMPLE_I2C.sim
........\........\....\SIMPLE_I2C.syn
........\........\....\SIMPLE_I2C__STRUCTURAL.sim
........\........\....\SIMPLE_I2C__STRUCTURAL.syn
........\chips\i2c_core
........\.....\i2c_core-optimized
........\workdirs\unisim
........\........\Virtex2_macro
........\........\WORK
........\chips
........\files
........\workdirs
i2c_core

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