fpga verilog hdl ，quartusii 9.0 ，2booth 4bit

mux4booth\db\mux4booth.asm.qmsg
.........\..\mux4booth.asm_labs.ddb
.........\..\mux4booth.cbx.xml
.........\..\mux4booth.cmp.bpm
.........\..\mux4booth.cmp.cdb
.........\..\mux4booth.cmp.ecobp
.........\..\mux4booth.cmp.hdb
.........\..\mux4booth.cmp.kpt
.........\..\mux4booth.cmp.logdb
.........\..\mux4booth.cmp.rdb
.........\..\mux4booth.cmp.tdb
.........\..\mux4booth.cmp0.ddb
.........\..\mux4booth.cmp2.ddb
.........\..\mux4booth.cmp_merge.kpt
.........\..\mux4booth.db_info
.........\..\mux4booth.eco.cdb
.........\..\mux4booth.eda.qmsg
.........\..\mux4booth.fit.qmsg
.........\..\mux4booth.hier_info
.........\..\mux4booth.hif
.........\..\mux4booth.lpc.html
.........\..\mux4booth.lpc.rdb
.........\..\mux4booth.lpc.txt
.........\..\mux4booth.map.bpm
.........\..\mux4booth.map.cdb
.........\..\mux4booth.map.ecobp
.........\..\mux4booth.map.hdb
.........\..\mux4booth.map.kpt
.........\..\mux4booth.map.logdb
.........\..\mux4booth.map.qmsg
.........\..\mux4booth.map_bb.cdb
.........\..\mux4booth.map_bb.hdb
.........\..\mux4booth.map_bb.logdb
.........\..\mux4booth.pre_map.cdb
.........\..\mux4booth.pre_map.hdb
.........\..\mux4booth.rpp.qmsg
.........\..\mux4booth.rtlv.hdb
.........\..\mux4booth.rtlv_sg.cdb
.........\..\mux4booth.rtlv_sg_swap.cdb
.........\..\mux4booth.sgate.rvd
.........\..\mux4booth.sgate_sm.rvd
.........\..\mux4booth.sgdiff.cdb
.........\..\mux4booth.sgdiff.hdb
.........\..\mux4booth.sld_design_entry.sci
.........\..\mux4booth.sld_design_entry_dsc.sci
.........\..\mux4booth.syn_hier_info
.........\..\mux4booth.tan.qmsg
.........\..\mux4booth.tis_db_list.ddb
.........\..\mux4booth_global_asgn_op.abo
.........\..\prev_cmp_mux4booth.asm.qmsg
.........\..\prev_cmp_mux4booth.eda.qmsg
.........\..\prev_cmp_mux4booth.fit.qmsg
.........\..\prev_cmp_mux4booth.map.qmsg
.........\..\prev_cmp_mux4booth.tan.qmsg
.........\incremental_db\compiled_partitions\mux4booth.root_partition.cmp.atm
.........\..............\...................\mux4booth.root_partition.cmp.dfp
.........\..............\...................\mux4booth.root_partition.cmp.hdbx
.........\..............\...................\mux4booth.root_partition.cmp.kpt
.........\..............\...................\mux4booth.root_partition.cmp.logdb
.........\..............\...................\mux4booth.root_partition.cmp.rcf
.........\..............\...................\mux4booth.root_partition.map.atm
.........\..............\...................\mux4booth.root_partition.map.dpi
.........\..............\...................\mux4booth.root_partition.map.hdbx
.........\..............\...................\mux4booth.root_partition.map.kpt
.........\..............\README
.........\mux4booth.asm.rpt
.........\mux4booth.done
.........\mux4booth.eda.rpt
.........\mux4booth.fit.rpt
.........\mux4booth.fit.smsg
.........\mux4booth.fit.summary
.........\mux4booth.flow.rpt
.........\mux4booth.map.rpt
.........\mux4booth.map.summary
.........\mux4booth.pin
.........\mux4booth.pof
.........\mux4booth.qpf
.........\mux4booth.qsf
.........\mux4booth.sof
.........\mux4booth.tan.rpt
.........\mux4booth.tan.summary
.........\mux4booth.v
.........\mux4booth.v.bak
.........\mux4booth_nativelink_simulation.rpt
.........\simulation\modelsim\gate_work\mux4booth\_primary.dat
.........\..........\........\.........\.........\_primary.dbs
.........\..........\........\.........\.........\_primary.vhd
.........\..........\........\.........\t_mul_4booth\_primary.dat
.........\..........\........\.........\............\_primary.dbs
.........\..........\........\.........\............\_primary.vhd
.........\..........\........\.........\_info
.........\..........\........\.........\.temp\sdfyjkye1
.........\..........\........\.........\_vmake
.........\..........\........\modelsim.ini
.........\..........\........\msim_transcript
.........\..........\........\mux4booth.sft
.........\..........\........\mux4booth.vo
.........\..........\........\mux4booth_modelsim.xrf
.........\..........\........\mux4booth_run_msim_gate_verilog.do
.........\..........\........\mux4booth_run_msim_gate_verilog.

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