FPGA-duty test procedures have been verified, their preparation, use verilog program

duty cycle\B_to_D.v
..........\B_to_D.v.bak
..........\db\add_sub_2ch.tdf
..........\..\add_sub_4ch.tdf
..........\..\add_sub_5ch.tdf
..........\..\add_sub_6ch.tdf
..........\..\add_sub_9ch.tdf
..........\..\add_sub_lkc.tdf
..........\..\add_sub_mkc.tdf
..........\..\altsyncram_es14.tdf
..........\..\altsyncram_mgq1.tdf
..........\..\altsyncram_qp14.tdf
..........\..\alt_u_div_46f.tdf
..........\..\alt_u_div_c5f.tdf
..........\..\alt_u_div_k5f.tdf
..........\..\alt_u_div_o5f.tdf
..........\..\alt_u_div_s5f.tdf
..........\..\cmpr_5cc.tdf
..........\..\cmpr_8cc.tdf
..........\..\cmpr_9cc.tdf
..........\..\cmpr_acc.tdf
..........\..\cntr_02j.tdf
..........\..\cntr_gui.tdf
..........\..\cntr_m4j.tdf
..........\..\cntr_qbi.tdf
..........\..\cntr_sbi.tdf
..........\..\cntr_ubi.tdf
..........\..\decode_rqf.tdf
..........\..\duty_cycle.amm.cdb
..........\..\duty_cycle.asm.qmsg
..........\..\duty_cycle.asm.rdb
..........\..\duty_cycle.asm_labs.ddb
..........\..\duty_cycle.cbx.xml
..........\..\duty_cycle.cmp.bpm
..........\..\duty_cycle.cmp.cdb
..........\..\duty_cycle.cmp.hdb
..........\..\duty_cycle.cmp.kpt
..........\..\duty_cycle.cmp.logdb
..........\..\duty_cycle.cmp.rdb
..........\..\duty_cycle.cmp0.ddb
..........\..\duty_cycle.cmp1.ddb
..........\..\duty_cycle.cmp2.ddb
..........\..\duty_cycle.cmp_merge.kpt
..........\..\duty_cycle.db_info
..........\..\duty_cycle.fit.qmsg
..........\..\duty_cycle.hier_info
..........\..\duty_cycle.hif
..........\..\duty_cycle.idb.cdb
..........\..\duty_cycle.lpc.html
..........\..\duty_cycle.lpc.rdb
..........\..\duty_cycle.lpc.txt
..........\..\duty_cycle.map.bpm
..........\..\duty_cycle.map.cdb
..........\..\duty_cycle.map.hdb
..........\..\duty_cycle.map.kpt
..........\..\duty_cycle.map.logdb
..........\..\duty_cycle.map.qmsg
..........\..\duty_cycle.map_bb.cdb
..........\..\duty_cycle.map_bb.hdb
..........\..\duty_cycle.map_bb.logdb
..........\..\duty_cycle.pre_map.cdb
..........\..\duty_cycle.pre_map.hdb
..........\..\duty_cycle.rtlv.hdb
..........\..\duty_cycle.rtlv_sg.cdb
..........\..\duty_cycle.rtlv_sg_swap.cdb
..........\..\duty_cycle.sgdiff.cdb
..........\..\duty_cycle.sgdiff.hdb
..........\..\duty_cycle.sld_design_entry.sci
..........\..\duty_cycle.sld_design_entry_dsc.sci
..........\..\duty_cycle.smart_action.txt
..........\..\duty_cycle.smp_dump.txt
..........\..\duty_cycle.sta.qmsg
..........\..\duty_cycle.sta.rdb
..........\..\duty_cycle.sta_cmp.8_slow.tdb
..........\..\duty_cycle.syn_hier_info
..........\..\duty_cycle.tis_db_list.ddb
..........\..\duty_cycle.tmw_info
..........\..\logic_util_heursitic.dat
..........\..\lpm_divide_1gm.tdf
..........\..\lpm_divide_3gm.tdf
..........\..\lpm_divide_7gm.tdf
..........\..\lpm_divide_rfm.tdf
..........\..\lpm_divide_vfm.tdf
..........\..\mux_7oc.tdf
..........\..\mux_aoc.tdf
..........\..\prev_cmp_duty_cycle.qmsg
..........\..\sign_div_unsign_5nh.tdf
..........\..\sign_div_unsign_9nh.tdf
..........\..\sign_div_unsign_bnh.tdf
..........\..\sign_div_unsign_dnh.tdf
..........\..\sign_div_unsign_hnh.tdf
..........\duty_cycle.asm.rpt
..........\duty_cycle.cdf
..........\duty_cycle.done
..........\duty_cycle.dpf
..........\duty_cycle.fit.rpt
..........\duty_cycle.fit.smsg
..........\duty_cycle.fit.summary
..........\duty_cycle.flow.rpt
..........\duty_cycle.jdi

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