altera vip, specific reference an427 documentation!

pip_example_design_3c120_vdk_v80
................................\3c120_host_board_pins.tcl
................................\altmemddr_bot.html
................................\altmemddr_bot.ppf
................................\altmemddr_bot.qip
................................\altmemddr_bot.v
................................\altmemddr_bot_advisor.ipa
................................\altmemddr_bot_auk_ddr_hp_controller_wrapper.v
................................\altmemddr_bot_controller_phy.v
................................\altmemddr_bot_example_driver.v
................................\altmemddr_bot_example_top.sdc
................................\altmemddr_bot_example_top.v
................................\altmemddr_bot_ex_lfsr8.v
................................\altmemddr_bot_phy.html
................................\altmemddr_bot_phy.qip
................................\altmemddr_bot_phy.v
................................\altmemddr_bot_phy_alt_mem_phy_ciii.v
................................\altmemddr_bot_phy_alt_mem_phy_pll_ciii.bsf
................................\altmemddr_bot_phy_alt_mem_phy_pll_ciii.ppf
................................\altmemddr_bot_phy_alt_mem_phy_pll_ciii.qip
................................\altmemddr_bot_phy_alt_mem_phy_pll_ciii.v
................................\altmemddr_bot_phy_alt_mem_phy_pll_ciii_bb.v
................................\altmemddr_bot_phy_alt_mem_phy_sequencer_wrapper.v
................................\altmemddr_bot_phy_autodetectedpins.tcl
................................\altmemddr_bot_phy_ddr_pins.tcl
................................\altmemddr_bot_phy_ddr_timing.sdc
................................\altmemddr_bot_phy_report_timing.tcl
................................\altmemddr_bot_phy_simgen_init.txt
................................\altmemddr_bot_pin_assignments.tcl
................................\altmemddr_controller_phy.v
................................\altmemddr_ex_lfsr8.v
................................\altmemddr_top.html
................................\altmemddr_top.ppf
................................\altmemddr_top.qip
................................\altmemddr_top.v
................................\altmemddr_top_advisor.ipa
................................\altmemddr_top_auk_ddr_hp_controller_wrapper.v
................................\altmemddr_top_controller_phy.v
................................\altmemddr_top_example_driver.v
................................\altmemddr_top_example_top.sdc
................................\altmemddr_top_example_top.v
................................\altmemddr_top_ex_lfsr8.v
................................\altmemddr_top_phy.html
................................\altmemddr_top_phy.qip
................................\altmemddr_top_phy.v
................................\altmemddr_top_phy_alt_mem_phy_ciii.v
................................\altmemddr_top_phy_alt_mem_phy_pll_ciii.bsf
................................\altmemddr_top_phy_alt_mem_phy_pll_ciii.ppf
................................\altmemddr_top_phy_alt_mem_phy_pll_ciii.qip
................................\altmemddr_top_phy_alt_mem_phy_pll_ciii.v
................................\altmemddr_top_phy_alt_mem_phy_pll_ciii_bb.v
................................\altmemddr_top_phy_alt_mem_phy_sequencer_wrapper.v
................................\altmemddr_top_phy_autodetectedpins.tcl
................................\altmemddr_top_phy_ddr_pins.tcl
................................\altmemddr_top_phy_ddr_timing.sdc
................................\altmemddr_top_phy_report_timing.tcl
................................\altmemddr_top_phy_simgen_init.txt
................................\altmemddr_top_pin_assignments.tcl
................................\altpll0.bsf
................................\altpll0.cmp
................................\altpll0.ppf
................................\altpll0.qip
................................\altpll0.vhd
................................\alt_mem_phy_defines.v
................................\alt_mem_phy_sequencer.vhd
................................\auk_ddr2_h

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