Divider using verilog achieve

fenpin5
.......\db
.......\..\add_sub_1nh.tdf
.......\..\fenpin5.asm.qmsg
.......\..\fenpin5.cbx.xml
.......\..\fenpin5.cmp.cdb
.......\..\fenpin5.cmp.hdb
.......\..\fenpin5.cmp.logdb
.......\..\fenpin5.cmp.rdb
.......\..\fenpin5.cmp.tdb
.......\..\fenpin5.cmp0.ddb
.......\..\fenpin5.db_info
.......\..\fenpin5.dbp
.......\..\fenpin5.eco.cdb
.......\..\fenpin5.eds_overflow
.......\..\fenpin5.fit.qmsg
.......\..\fenpin5.fnsim.cdb
.......\..\fenpin5.fnsim.hdb
.......\..\fenpin5.fnsim.qmsg
.......\..\fenpin5.hier_info
.......\..\fenpin5.hif
.......\..\fenpin5.map.cdb
.......\..\fenpin5.map.hdb
.......\..\fenpin5.map.logdb
.......\..\fenpin5.map.qmsg
.......\..\fenpin5.pre_map.cdb
.......\..\fenpin5.pre_map.hdb
.......\..\fenpin5.psp
.......\..\fenpin5.pss
.......\..\fenpin5.rtlv.hdb
.......\..\fenpin5.rtlv_sg.cdb
.......\..\fenpin5.rtlv_sg_swap.cdb
.......\..\fenpin5.sgdiff.cdb
.......\..\fenpin5.sgdiff.hdb
.......\..\fenpin5.sim.cvwf
.......\..\fenpin5.sim.hdb
.......\..\fenpin5.sim.qmsg
.......\..\fenpin5.sim.rdb
.......\..\fenpin5.simfam
.......\..\fenpin5.sld_design_entry.sci
.......\..\fenpin5.sld_design_entry_dsc.sci
.......\..\fenpin5.syn_hier_info
.......\..\fenpin5.tan.qmsg
.......\..\fenpin5.tis_db_list.ddb
.......\..\prev_cmp_fenpin5.asm.qmsg
.......\..\prev_cmp_fenpin5.fit.qmsg
.......\..\prev_cmp_fenpin5.map.qmsg
.......\..\prev_cmp_fenpin5.qmsg
.......\..\prev_cmp_fenpin5.tan.qmsg
.......\..\wed.wsf
.......\fenpin5.asm.rpt
.......\fenpin5.done
.......\fenpin5.fit.rpt
.......\fenpin5.fit.summary
.......\fenpin5.flow.rpt
.......\fenpin5.map.rpt
.......\fenpin5.map.summary
.......\fenpin5.pin
.......\fenpin5.pof
.......\fenpin5.qpf
.......\fenpin5.qsf
.......\fenpin5.qws
.......\fenpin5.sim.rpt
.......\fenpin5.tan.rpt
.......\fenpin5.tan.summary
.......\fenpin5.v
.......\fenpin5.vwf

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