verilog HDL code

Verilog HDL程序设计实例详解A\Verilog HDL程序设计实例详解 光盘\Chapter-13\risc8\alu.v
............................\................................\..........\.....\basic.rom
............................\................................\..........\.....\cpu.v
............................\................................\..........\.....\cpu_test.v
............................\................................\..........\.....\dram.v
............................\................................\..........\.....\exp.v
............................\................................\..........\.....\idec.v
............................\................................\..........\.....\pram.v
............................\................................\..........\.....\regs.v
............................\................................\..........\.....\risc8.cr.mti
............................\................................\..........\.....\risc8.mpf
............................\................................\..........\.....\risc8.vcd
............................\................................\..........\.....\sindata.hex
............................\................................\..........\.....\transcript
............................\................................\..........\.....\vsim.wlf
............................\................................\..........\.....\chart\图13-11.bmp
............................\................................\..........\.....\.....\图13-13.bmp
............................\................................\..........\.....\.....\图13-15.bmp
............................\................................\..........\.....\.....\图13-16.bmp
............................\................................\..........\.....\.....\图13-17.bmp
............................\................................\..........\.....\.....\图13-18.bmp
............................\................................\..........\.....\.....\图13-20.bmp
............................\................................\..........\.....\.....\图13-6.bmp
............................\................................\..........\.....\.....\图13-7.bmp
............................\................................\..........\.....\.....\图13-9.bmp
............................\................................\..........\.....\.....\表13-1.bmp
............................\................................\..........\.....\wave\alu.bmp
............................\................................\..........\.....\....\cpu-1.bmp
............................\................................\..........\.....\....\cpu-2.bmp
............................\................................\..........\.....\....\cpu_test.bmp
............................\................................\..........\.....\....\exp.bmp
............................\................................\..........\.....\....\idec.bmp
............................\................................\..........\.....\....\pram.bmp
............................\................................\..........\.....\....\regs.bmp
............................\................................\..........\.....\.ork\_info
............................\................................\..........\.....\....\risc8.vcd
............................\................................\..........\.....\....\alu\_primary.dat
............................\................................\..........\.....\....\...\_primary.vhd
............................\................................\..........\.....\....\...\verilog.asm
............................\................................\..........\.....\....\cpu\_primary.dat
............................\................................\..........\.....\....\...\_primary.vhd
............................\................................\..........\.....\....\...\verilog.asm
............................\................................\..........\.....\....\..._test\_primary.dat
............................\................................\........

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