This application note describes the implementation of SERDES Framer Interface Level 5 (SFI-5) [Ref 1] in a Virtex-6 XC6VLX240T FPGA. SFI-5 is a standard defined by the Optical Internetworking Forum (OIF). The interface must operate bidirectionally at a payload data rate of 40 Gb/s with 0–25 forward error correction (FEC) overhead, up to a maximum of 50 Gb/s. The interface consists of 17 bidirectional GTX transceivers and logic to compensate skew differences between the transmission paths of the data channels.

XAPP882
.......\Bitfile
.......\.......\sfi5.bit
.......\Chipscope
.......\.........\chipscope_icon.ngc
.......\.........\chipscope_icon.v
.......\.........\chipscope_ila.ngc
.......\.........\chipscope_ila.v
.......\.........\chipscope_vio.ngc
.......\.........\chipscope_vio.v
.......\.........\SFI5_DEMO.cpj
.......\Design
.......\......\counter_128.v
.......\......\counter_32bit.v
.......\......\counter_64.v
.......\......\gtx_wrapper.v
.......\......\gtx_wrapper_gtx.v
.......\......\sfi5_if_v6_16bit.v
.......\......\sfi5_reset_rx.v
.......\......\sfi5_reset_tx.v
.......\......\sfi5_rx_barrel_shifter_16bit.v
.......\......\sfi5_rx_data_sync.v
.......\......\sfi5_rx_frame_sync.v
.......\......\sfi5_rx_if_v6_16bit.v
.......\......\sfi5_tx_deskew_channel.v
.......\......\tx_sync.v
.......\Hardware_Testbench
.......\..................\prbs31_gen.v
.......\..................\sfi5_ml623_demo.v
.......\Implementation
.......\..............\run_syn
.......\..............\sfi5.cmd
.......\..............\sfi5.prj
.......\..............\sfi5_ml623_demo.ucf
.......\readme.txt
.......\Simulation
.......\..........\SFI5_V6_16BIT_TB.v
.......\..........\sim
.......\..........\...\glbl.v
.......\..........\...\run_sim.do
.......\..........\...\sfi5_wave.do
.......\..........\simple_pattern0.v
.......\..........\simple_pattern1.v

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