Using verilog hardware description language prepared by the SPI interface program, verified by simulation.

spi_m\spi_m.done
.....\spi_m.flow.rpt
.....\spi_m.map.rpt
.....\spi_m.map.summary
.....\spi_m.qpf
.....\spi_m.qsf
.....\spi_m.qws
.....\spi_m.sim.rpt
.....\spi_m.v
.....\spi_m.v.bak
.....\spi_m.vwf
.....\db\mux_joc.tdf
.....\..\prev_cmp_spi_m.map.qmsg
.....\..\prev_cmp_spi_m.qmsg
.....\..\prev_cmp_spi_m.sim.qmsg
.....\..\spi_m.cbx.xml
.....\..\spi_m.cmp.rdb
.....\..\spi_m.dbp
.....\..\spi_m.db_info
.....\..\spi_m.eco.cdb
.....\..\spi_m.eds_overflow
.....\..\spi_m.fnsim.cdb
.....\..\spi_m.fnsim.hdb
.....\..\spi_m.fnsim.qmsg
.....\..\spi_m.hier_info
.....\..\spi_m.hif
.....\..\spi_m.map.bpm
.....\..\spi_m.map.cdb
.....\..\spi_m.map.ecobp
.....\..\spi_m.map.hdb
.....\..\spi_m.map.logdb
.....\..\spi_m.map.qmsg
.....\..\spi_m.map_bb.cdb
.....\..\spi_m.map_bb.hdb
.....\..\spi_m.map_bb.logdb
.....\..\spi_m.pre_map.cdb
.....\..\spi_m.pre_map.hdb
.....\..\spi_m.psp
.....\..\spi_m.pss
.....\..\spi_m.rtlv.hdb
.....\..\spi_m.rtlv_sg.cdb
.....\..\spi_m.rtlv_sg_swap.cdb
.....\..\spi_m.sgdiff.cdb
.....\..\spi_m.sgdiff.hdb
.....\..\spi_m.sim.cvwf
.....\..\spi_m.sim.hdb
.....\..\spi_m.sim.qmsg
.....\..\spi_m.sim.rdb
.....\..\spi_m.simfam
.....\..\spi_m.sim_ori.vwf
.....\..\spi_m.sld_design_entry.sci
.....\..\spi_m.sld_design_entry_dsc.sci
.....\..\spi_m.syn_hier_info
.....\..\spi_m.tis_db_list.ddb
.....\..\wed.wsf
.....\db
spi_m

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