Open 8bit cpu IP from Lattice.

LatticeMico8_v3_1_VHDL\models
......................\......\e2
......................\......\..\sim
......................\......\..\...\ORCACOMP.vhd
......................\......\..\...\ORCA_CMB.vhd
......................\......\..\...\ORCA_CNT.vhd
......................\......\..\...\ORCA_IO.vhd
......................\......\..\...\ORCA_LUT.vhd
......................\......\..\...\ORCA_MEM.vhd
......................\......\..\...\ORCA_MISC.vhd
......................\......\..\...\ORCA_SEQ.vhd
......................\......\..\...\pmi_def.vhd
......................\......\..\...\prom.vhd
......................\......\..\syn
......................\......\..\...\ec.vhd
......................\......\pmi_work
......................\......\........\@add@sign
......................\......\........\.........\verilog.psm
......................\......\........\.........\_primary.dat
......................\......\........\.........\_primary.vhd
......................\......\........\@add@un@sign
......................\......\........\............\verilog.psm
......................\......\........\............\_primary.dat
......................\......\........\............\_primary.vhd
......................\......\........\@mult@add@sub
......................\......\........\.............\verilog.psm
......................\......\........\.............\_primary.dat
......................\......\........\.............\_primary.vhd
......................\......\........\@mult@sign
......................\......\........\..........\verilog.psm
......................\......\........\..........\_primary.dat
......................\......\........\..........\_primary.vhd
......................\......\........\@mult@sign@pipe
......................\......\........\...............\verilog.psm
......................\......\........\...............\_primary.dat
......................\......\........\...............\_primary.vhd
......................\......\........\@mult@un@sign
......................\......\........\.............\verilog.psm
......................\......\........\.............\_primary.dat
......................\......\........\.............\_primary.vhd
......................\......\........\@mult@un@sign@pipe
......................\......\........\..................\verilog.psm
......................\......\........\..................\_primary.dat
......................\......\........\..................\_primary.vhd
......................\......\........\@sub@sign
......................\......\........\.........\verilog.psm
......................\......\........\.........\_primary.dat
......................\......\........\.........\_primary.vhd
......................\......\........\@sub@un@sign
......................\......\........\............\verilog.psm
......................\......\........\............\_primary.dat
......................\......\........\............\_primary.vhd
......................\......\........\pmi_add
......................\......\........\.......\verilog.psm
......................\......\........\.......\_primary.dat
......................\......\........\.......\_primary.vhd
......................\......\........\pmi_addsub
......................\......\........\..........\verilog.psm
......................\......\........\..........\_primary.dat
......................\......\........\..........\_primary.vhd
......................\......\........\pmi_addsub_sign
......................\......\........\...............\verilog.psm
......................\......\........\...............\_primary.dat
......................\......\........\...............\_primary.vhd
......................\......\........\pmi_addsub_unsign
......................\......\........\.................\verilog.psm
......................\......\........\.................\_primary.dat
......................\......\........\.................\_primary.vhd
......................\......\........\pmi_add_sign
......................\......\........\............\verilog.psm
......................\......\........\........

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