KEY program written using VHDL, use and xilinx development board.

03.Anvyl_KYPD_SEG_Demo
......................\4x4键盘 & 7段数码管 Demo On Anvyl.pdf
......................\bitfile
......................\.......\Anvyl_kypd_seg.bit
......................\project
......................\.......\Anvyl_kypd_seven_seg
......................\.......\....................\Decoder.cmd_log
......................\.......\....................\Decoder.vhd
......................\.......\....................\_xmsgs
......................\.......\....................\......\ngcbuild.xmsgs
......................\.......\....................\......\pn_parser.xmsgs
......................\.......\....................\clock_divider.vhd
......................\.......\....................\counter.vhd
......................\.......\....................\cs1.cdc
......................\.......\....................\ipcore_dir
......................\.......\....................\..........\_xmsgs
......................\.......\....................\..........\......\cg.xmsgs
......................\.......\....................\..........\......\pn_parser.xmsgs
......................\.......\....................\..........\blk_mem_gen_ds512.pdf
......................\.......\....................\..........\blk_mem_gen_v6_3_readme.txt
......................\.......\....................\..........\coregen.cgp
......................\.......\....................\..........\create_seg_data_ram.tcl
......................\.......\....................\..........\edit_seg_data_ram.tcl
......................\.......\....................\..........\seg_data_ram
......................\.......\....................\..........\............\example_design
......................\.......\....................\..........\............\..............\bmg_wrapper.vhd
......................\.......\....................\..........\............\..............\seg_data_ram_top.ucf
......................\.......\....................\..........\............\..............\seg_data_ram_top.vhd
......................\.......\....................\..........\............\..............\seg_data_ram_top.xdc
......................\.......\....................\..........\............\implement
......................\.......\....................\..........\............\.........\implement.bat
......................\.......\....................\..........\............\.........\implement.sh
......................\.......\....................\..........\............\.........\planAhead_rdn.bat
......................\.......\....................\..........\............\.........\planAhead_rdn.sh
......................\.......\....................\..........\............\.........\planAhead_rdn.tcl
......................\.......\....................\..........\............\.........\xst.prj
......................\.......\....................\..........\............\.........\xst.scr
......................\.......\....................\..........\............\simulation
......................\.......\....................\..........\............\..........\addr_gen.vhd
......................\.......\....................\..........\............\..........\bmg_stim_gen.vhd
......................\.......\....................\..........\............\..........\bmg_tb_pkg.vhd
......................\.......\....................\..........\............\..........\bmg_tb_synth.vhd
......................\.......\....................\..........\............\..........\bmg_tb_top.vhd
......................\.......\....................\..........\............\..........\checker.vhd
......................\.......\....................\..........\............\..........\data_gen.vhd
......................\.......\....................\..........\............\..........\functional
......................\.......\....................\..........\............\..........\..........\isim_tcl_cmds.tcl
......................\.......\....................\..........\............\..........\..........\simulate_isim.sh
......................\.......\....................\..........\.....

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