I use FPGA blackjack game programs, including the top-level circuit sch file gives each module using VHDL language

100Hz.vhd
AvoidS.vhd
black_new.vhd
Flash_4.vhd
FPJ.vhd
Reg44.vhd
RorR.vhd
ScreenChoose.vhd
test_fenpin.vhd
test_for_curr.vhd
Top_Sch.sch
Translate.vhd

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