A function of the FPGA to achieve a specific program, the use of VHDL language for FPGA exclude the impact of other chip detection circuit is working properly

INOUT\10.mcs
.....\10.prm
.....\10.sig
.....\device_usage_statistics.html
.....\INOUT.ise
.....\INOUT.ise_ISE_Backup
.....\INOUT.ntrc_log
.....\pepExtractor.prj
.....\test.bgn
.....\test.bit
.....\TEST.bld
.....\TEST.cel
.....\TEST.cmd_log
.....\test.drc
.....\TEST.lfp
.....\TEST.lso
.....\TEST.ncd
.....\TEST.ngc
.....\TEST.ngd
.....\TEST.ngr
.....\TEST.pad
.....\TEST.par
.....\TEST.pcf
.....\TEST.prj
.....\TEST.stx
.....\TEST.syr
.....\test.twr
.....\test.twx
.....\TEST.ucf
.....\TEST.unroutes
.....\TEST.ut
.....\TEST.vhd
.....\TEST.xpi
.....\TEST.xst
.....\TEST_guide.ncd
.....\TEST_map.map
.....\TEST_map.mrp
.....\TEST_map.ncd
.....\TEST_map.ngm
.....\TEST_pad.csv
.....\TEST_pad.txt
.....\TEST_prev_built.ngd
.....\TEST_summary.html
.....\TEST_summary.xml
.....\TEST_usage.xml
.....\TEST_vhdl.prj
.....\xst\dump.xst\TEST.prj\ntrc.scr
.....\...\work\hdllib.ref
.....\...\....\hdpdeps.ref
.....\...\....\sub00\vhpl00.vho
.....\...\....\.....\vhpl01.vho
.....\_impact.cmd
.....\_impact.log
.....\.ngo\netlist.lst
.....\_pace.ucf
.....\.xmsgs\bitgen.xmsgs
.....\......\map.xmsgs
.....\......\ngdbuild.xmsgs
.....\......\par.xmsgs
.....\......\trce.xmsgs
.....\......\xst.xmsgs
.....\xst\dump.xst\TEST.prj\ngx\notopt
.....\...\........\........\...\opt
.....\...\........\........\ngx
.....\...\........\TEST.prj
.....\...\work\sub00
.....\...\dump.xst
.....\...\projnav.tmp
.....\...\work
.....\xst
.....\_ngo
.....\_xmsgs
INOUT

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