Advanced experimental _12_DA [TLC5615] _1: By DA output sine wave, frequency 1KHz

进阶实验_12_DA[TLC5615]_1：通过DA输出正弦波，频率1KHz
.....................................................\Modelsim
.....................................................\........\DAC.cr.mti
.....................................................\........\DAC.mpf
.....................................................\........\sim.do
.....................................................\........\vsim.wlf
.....................................................\........\work
.....................................................\........\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
.....................................................\........\....\..........................................\verilog.asm
.....................................................\........\....\..........................................\_primary.dat
.....................................................\........\....\..........................................\_primary.vhd
.....................................................\........\....\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
.....................................................\........\....\...............................................\_primary.dat
.....................................................\........\....\...............................................\_primary.vhd
.....................................................\........\....\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n
.....................................................\........\....\...........................................................\verilog.asm
.....................................................\........\....\...........................................................\_primary.dat
.....................................................\........\....\...........................................................\_primary.vhd
.....................................................\........\....\@d@a@c_5615_@c@t@l
.....................................................\........\....\..................\verilog.asm
.....................................................\........\....\..................\_primary.dat
.....................................................\........\....\..................\_primary.vhd
.....................................................\........\....\@d@a@c_5615_@c@t@l_tb
.....................................................\........\....\.....................\_primary.dat
.....................................................\........\....\.....................\_primary.vhd
.....................................................\........\....\@d@a@c_@s@i@n@e_1@k
.....................................................\........\....\...................\verilog.asm
.....................................................\........\....\...................\_primary.dat
.....................................................\........\....\...................\_primary.vhd
.....................................................\........\....\@d@a@c_@s@i@n@e_1@k_tb
.....................................................\........\....\......................\verilog.asm
.....................................................\........\....\......................\_primary.dat
.....................................................\........\....\......................\_primary.vhd
.....................................................\........\....\@m@f_cycloneiii_pll
.....................................................\........\....\...................\_primary.dat
.....................................................\........\....\...................\_primary.vhd
.....................................................\........\....\@m@f_pll_reg
.....................................................\........\....\............\_primary.dat
.....................................................\........\....\............\_primary.vhd
.....................................................\........\....\@m@f_stratixiii_pll
.....................................................\........\....\...................\_prim

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