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ddr3_12.1V

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-07-13
  • Size : 17.98mb
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  • Author :An***
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Introduction - If you have any usage issues, please Google them yourself
DDR3 Simulation environment
Packet file list
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ddr3_12.1V
..........\db
..........\..\ddr3.db_info
..........\..\ddr3.qns
..........\..\ddr3.sas
..........\..\ddr3.sld_design_entry.sci
..........\ddr3
..........\ddr3.bsf
..........\ddr3.cmp
..........\ddr3.ppf
..........\ddr3.qip
..........\ddr3.qpf
..........\ddr3.qsf
..........\ddr3.qws
..........\ddr3.sip
..........\ddr3.sopcinfo
..........\ddr3.spd
..........\ddr3.vhd
..........\....\afi_mux_ddr3_ddrx.v
..........\....\altdq_dqs2_stratixv.sv
..........\....\altera_avalon_mm_bridge.v
..........\....\altera_avalon_packets_to_master.v
..........\....\altera_avalon_sc_fifo.v
..........\....\altera_avalon_st_bytes_to_packets.v
..........\....\altera_avalon_st_clock_crosser.v
..........\....\altera_avalon_st_idle_inserter.v
..........\....\altera_avalon_st_idle_remover.v
..........\....\altera_avalon_st_jtag_interface.sdc
..........\....\altera_avalon_st_jtag_interface.v
..........\....\altera_avalon_st_packets_to_bytes.v
..........\....\altera_avalon_st_pipeline_base.v
..........\....\altera_jtag_dc_streaming.v
..........\....\altera_jtag_sld_node.v
..........\....\altera_jtag_streaming.v
..........\....\altera_mem_if_dll_stratixv.sv
..........\....\altera_mem_if_oct_stratixv.sv
..........\....\altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst.v
..........\....\altera_mem_if_sequencer_cpu_no_ifdef_params_synth_cpu_inst_test_bench.v
..........\....\altera_mem_if_sequencer_mem_no_ifdef_params.sv
..........\....\altera_merlin_arbitrator.sv
..........\....\altera_merlin_burst_uncompressor.sv
..........\....\altera_merlin_master_agent.sv
..........\....\altera_merlin_master_translator.sv
..........\....\altera_merlin_slave_agent.sv
..........\....\altera_merlin_slave_translator.sv
..........\....\altera_merlin_traffic_limiter.sv
..........\....\altera_pli_streaming.v
..........\....\altera_reset_controller.sdc
..........\....\altera_reset_controller.v
..........\....\altera_reset_synchronizer.v
..........\....\alt_mem_ddrx_addr_cmd.v
..........\....\alt_mem_ddrx_addr_cmd_wrap.v
..........\....\alt_mem_ddrx_arbiter.v
..........\....\alt_mem_ddrx_axi_st_converter.v
..........\....\alt_mem_ddrx_buffer.v
..........\....\alt_mem_ddrx_buffer_manager.v
..........\....\alt_mem_ddrx_burst_gen.v
..........\....\alt_mem_ddrx_burst_tracking.v
..........\....\alt_mem_ddrx_cmd_gen.v
..........\....\alt_mem_ddrx_controller.v
..........\....\alt_mem_ddrx_controller_st_top.v
..........\....\alt_mem_ddrx_csr.v
..........\....\alt_mem_ddrx_dataid_manager.v
..........\....\alt_mem_ddrx_ddr2_odt_gen.v
..........\....\alt_mem_ddrx_ddr3_odt_gen.v
..........\....\alt_mem_ddrx_define.iv
..........\....\alt_mem_ddrx_ecc_decoder.v
..........\....\alt_mem_ddrx_ecc_decoder_32_syn.v
..........\....\alt_mem_ddrx_ecc_decoder_64_syn.v
..........\....\alt_mem_ddrx_ecc_encoder.v
..........\....\alt_mem_ddrx_ecc_encoder_32_syn.v
..........\....\alt_mem_ddrx_ecc_encoder_64_syn.v
..........\....\alt_mem_ddrx_ecc_encoder_decoder_wrapper.v
..........\....\alt_mem_ddrx_fifo.v
..........\....\alt_mem_ddrx_input_if.v
..........\....\alt_mem_ddrx_list.v
..........\....\alt_mem_ddrx_lpddr2_addr_cmd.v
..........\....\alt_mem_ddrx_mm_st_converter.v
..........\....\alt_mem_ddrx_odt_gen.v
..........\....\alt_mem_ddrx_rank_timer.v
..........\....\alt_mem_ddrx_rdata_path.v
..........\....\alt_mem_ddrx_rdwr_data_tmg.v
..........\....\alt_mem_ddrx_sideband.v
..........\....\alt_mem_ddrx_tbp.v
..........\....\alt_mem_ddrx_timing_param.v
..........\....\alt_mem_ddrx_wdata_path.v
..........\....\alt_mem_if_nextgen_ddr3_controller_core.sv
..........\....\ddr3_0002.v
..........\....\ddr3_c0.v
..........\....\ddr3_dmaster.v
..........\....\ddr3_dmaster_b2p_adapter.v
..........\....\ddr3_dmaster_p2b_adapter.v
..........\....\ddr3_dmaster_timing_adt.v
..........\....\ddr3_p0.ppf
..........\....\ddr3_p0.sdc
..........\....\ddr3_p0.sv
..........\....\ddr3_p0_acv_ldc.v
..........\....\ddr3_p0_addr_cmd_datapath.v
..........\....\ddr3_p0_addr_cmd_ldc_pad.v
..........\....\ddr3_p0_addr_cmd_ldc_pads.v
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