Learning FPGA students can see, this code is written using VHDL language sequence generator, not only can learn QUARTUS software, also can better enhance the digital circuit design.

seq_sig_generator_ok_序列发生器\6.0.txt
...............................\db\seq_sig_generator.asm.qmsg
...............................\..\seq_sig_generator.asm_labs.ddb
...............................\..\seq_sig_generator.cbx.xml
...............................\..\seq_sig_generator.cmp.cdb
...............................\..\seq_sig_generator.cmp.hdb
...............................\..\seq_sig_generator.cmp.kpt
...............................\..\seq_sig_generator.cmp.logdb
...............................\..\seq_sig_generator.cmp.rdb
...............................\..\seq_sig_generator.cmp.tdb
...............................\..\seq_sig_generator.cmp0.ddb
...............................\..\seq_sig_generator.dbp
...............................\..\seq_sig_generator.db_info
...............................\..\seq_sig_generator.eco.cdb
...............................\..\seq_sig_generator.eds_overflow
...............................\..\seq_sig_generator.fit.qmsg
...............................\..\seq_sig_generator.hier_info
...............................\..\seq_sig_generator.hif
...............................\..\seq_sig_generator.map.cdb
...............................\..\seq_sig_generator.map.hdb
...............................\..\seq_sig_generator.map.logdb
...............................\..\seq_sig_generator.map.qmsg
...............................\..\seq_sig_generator.pre_map.cdb
...............................\..\seq_sig_generator.pre_map.hdb
...............................\..\seq_sig_generator.psp
...............................\..\seq_sig_generator.rtlv.hdb
...............................\..\seq_sig_generator.rtlv_sg.cdb
...............................\..\seq_sig_generator.rtlv_sg_swap.cdb
...............................\..\seq_sig_generator.sgdiff.cdb
...............................\..\seq_sig_generator.sgdiff.hdb
...............................\..\seq_sig_generator.signalprobe.cdb
...............................\..\seq_sig_generator.sim.hdb
...............................\..\seq_sig_generator.sim.qmsg
...............................\..\seq_sig_generator.sim.rdb
...............................\..\seq_sig_generator.sim_ori.vwf
...............................\..\seq_sig_generator.sld_design_entry.sci
...............................\..\seq_sig_generator.sld_design_entry_dsc.sci
...............................\..\seq_sig_generator.smp_dump.txt
...............................\..\seq_sig_generator.syn_hier_info
...............................\..\seq_sig_generator.tan.qmsg
...............................\..\wed.zsf
...............................\ok.txt
...............................\seq_sig_generator.asm.rpt
...............................\seq_sig_generator.done
...............................\seq_sig_generator.fit.rpt
...............................\seq_sig_generator.fit.smsg
...............................\seq_sig_generator.fit.summary
...............................\seq_sig_generator.flow.rpt
...............................\seq_sig_generator.map.rpt
...............................\seq_sig_generator.map.summary
...............................\seq_sig_generator.pin
...............................\seq_sig_generator.pof
...............................\seq_sig_generator.qpf
...............................\seq_sig_generator.qsf
...............................\seq_sig_generator.qws
...............................\seq_sig_generator.sim.rpt
...............................\seq_sig_generator.tan.rpt
...............................\seq_sig_generator.tan.summary
...............................\seq_sig_generator.vhd
...............................\seq_sig_generator.vwf
...............................\seq_sig_generator程序逐行解释.doc
...............................\db
seq_sig_generator_ok_序列发生器

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