FPGA-based VGA display, you can change the display according to the different needs of the graphics.

EX5\db\logic_util_heursitic.dat
...\..\prev_cmp_VGA_8_VERILOG.qmsg
...\..\VGA_8_VERILOG.asm.qmsg
...\..\VGA_8_VERILOG.asm.rdb
...\..\VGA_8_VERILOG.asm_labs.ddb
...\..\VGA_8_VERILOG.cbx.xml
...\..\VGA_8_VERILOG.cmp.cdb
...\..\VGA_8_VERILOG.cmp.hdb
...\..\VGA_8_VERILOG.cmp.idb
...\..\VGA_8_VERILOG.cmp.kpt
...\..\VGA_8_VERILOG.cmp.logdb
...\..\VGA_8_VERILOG.cmp.rdb
...\..\VGA_8_VERILOG.cmp0.ddb
...\..\VGA_8_VERILOG.db_info
...\..\VGA_8_VERILOG.eda.qmsg
...\..\VGA_8_VERILOG.fit.qmsg
...\..\VGA_8_VERILOG.hier_info
...\..\VGA_8_VERILOG.hif
...\..\VGA_8_VERILOG.ipinfo
...\..\VGA_8_VERILOG.lpc.html
...\..\VGA_8_VERILOG.lpc.rdb
...\..\VGA_8_VERILOG.lpc.txt
...\..\VGA_8_VERILOG.map.cdb
...\..\VGA_8_VERILOG.map.hdb
...\..\VGA_8_VERILOG.map.logdb
...\..\VGA_8_VERILOG.map.qmsg
...\..\VGA_8_VERILOG.map.rdb
...\..\VGA_8_VERILOG.pre_map.cdb
...\..\VGA_8_VERILOG.pre_map.hdb
...\..\VGA_8_VERILOG.qns
...\..\VGA_8_VERILOG.root_partition.map.reg_db.cdb
...\..\VGA_8_VERILOG.routing.rdb
...\..\VGA_8_VERILOG.rtlv.hdb
...\..\VGA_8_VERILOG.rtlv_sg.cdb
...\..\VGA_8_VERILOG.rtlv_sg_swap.cdb
...\..\VGA_8_VERILOG.sas
...\..\VGA_8_VERILOG.sgdiff.cdb
...\..\VGA_8_VERILOG.sgdiff.hdb
...\..\VGA_8_VERILOG.sld_design_entry.sci
...\..\VGA_8_VERILOG.sld_design_entry_dsc.sci
...\..\VGA_8_VERILOG.smart_action.txt
...\..\VGA_8_VERILOG.sta.qmsg
...\..\VGA_8_VERILOG.sta.rdb
...\..\VGA_8_VERILOG.sta_cmp.5_slow.tdb
...\..\VGA_8_VERILOG.syn_hier_info
...\..\VGA_8_VERILOG.taw.rdb
...\..\VGA_8_VERILOG.tis_db_list.ddb
...\..\VGA_8_VERILOG.vpr.ammdb
...\incremental_db\compiled_partitions\VGA_8_VERILOG.db_info
...\..............\...................\VGA_8_VERILOG.root_partition.map.kpt
...\..............\README
...\output_files\VGA_8_VERILOG.asm.rpt
...\............\VGA_8_VERILOG.done
...\............\VGA_8_VERILOG.eda.rpt
...\............\VGA_8_VERILOG.fit.rpt
...\............\VGA_8_VERILOG.fit.smsg
...\............\VGA_8_VERILOG.fit.summary
...\............\VGA_8_VERILOG.flow.rpt
...\............\VGA_8_VERILOG.jdi
...\............\VGA_8_VERILOG.map.rpt
...\............\VGA_8_VERILOG.map.summary
...\............\VGA_8_VERILOG.pin
...\............\VGA_8_VERILOG.pof
...\............\VGA_8_VERILOG.sta.rpt
...\............\VGA_8_VERILOG.sta.summary
...\simulation\modelsim\modelsim.ini
...\..........\........\msim_transcript
...\..........\........\rtl_work\@v@g@a_8_@v@e@r@i@l@o@g\verilog.prw
...\..........\........\........\.......................\verilog.psm
...\..........\........\........\.......................\_primary.dat
...\..........\........\........\.......................\_primary.dbs
...\..........\........\........\.......................\_primary.vhd
...\..........\........\........\......................._vlg_tst\verilog.prw
...\..........\........\........\...............................\verilog.psm
...\..........\........\........\...............................\_primary.dat
...\..........\........\........\...............................\_primary.dbs
...\..........\........\........\...............................\_primary.vhd
...\..........\........\........\_info
...\..........\........\........\_vmake
...\..........\........\VGA_8_VERILOG.sft
...\..........\........\VGA_8_VERILOG.vo
...\..........\........\VGA_8_VERILOG.vt
...\..........\........\VGA_8_VERILOG.vt.bak
...\..........\........\VGA_8_VERILOG_modelsim.xrf
...\..........\........\VGA_8_VERILOG_run_msim_rtl_verilog.do
...\..........\........\VGA_8_VERILOG_v.sdo
...\..........\........\vsim.wlf
...\VGA_8_VERILOG.jdi
...\VGA_8_VERILOG.qpf
...\VGA_8_VERILOG.qsf
...\VGA_8_VERILOG.qws
...\VGA_8_VERILOG.sdc
...\VGA_8_VERILOG.v
...\VGA_8_VERILOG.v.bak
...\VGA_8_VERILOG_nativelink_simulation.rpt
...\simulation\modelsim\rtl_work\@v@g@a_8_@v@e@r@i@l@o@g
...\..........\........\........\@v@g@a_8_@v@e@r@i@l@o@g_vlg_tst
...\..........\........\........\_temp
...\..........\........\rtl_work
...\incremental_db\compiled_partitions

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