FPGA-based 16-bit multiplier, getting started can be a good look.

EX4\db\logic_util_heursitic.dat
...\..\MUX_16.asm.qmsg
...\..\MUX_16.asm.rdb
...\..\MUX_16.asm_labs.ddb
...\..\MUX_16.cbx.xml
...\..\MUX_16.cmp.cdb
...\..\MUX_16.cmp.hdb
...\..\MUX_16.cmp.idb
...\..\MUX_16.cmp.kpt
...\..\MUX_16.cmp.logdb
...\..\MUX_16.cmp.rdb
...\..\MUX_16.cmp0.ddb
...\..\MUX_16.db_info
...\..\MUX_16.eda.qmsg
...\..\MUX_16.fit.qmsg
...\..\MUX_16.hier_info
...\..\MUX_16.hif
...\..\MUX_16.ipinfo
...\..\MUX_16.lpc.html
...\..\MUX_16.lpc.rdb
...\..\MUX_16.lpc.txt
...\..\MUX_16.map.cdb
...\..\MUX_16.map.hdb
...\..\MUX_16.map.logdb
...\..\MUX_16.map.qmsg
...\..\MUX_16.map.rdb
...\..\MUX_16.pre_map.cdb
...\..\MUX_16.pre_map.hdb
...\..\MUX_16.qns
...\..\MUX_16.root_partition.map.reg_db.cdb
...\..\MUX_16.routing.rdb
...\..\MUX_16.rtlv.hdb
...\..\MUX_16.rtlv_sg.cdb
...\..\MUX_16.rtlv_sg_swap.cdb
...\..\MUX_16.sas
...\..\MUX_16.sgdiff.cdb
...\..\MUX_16.sgdiff.hdb
...\..\MUX_16.sld_design_entry.sci
...\..\MUX_16.sld_design_entry_dsc.sci
...\..\MUX_16.smart_action.txt
...\..\MUX_16.sta.qmsg
...\..\MUX_16.sta.rdb
...\..\MUX_16.sta_cmp.5_slow.tdb
...\..\MUX_16.syn_hier_info
...\..\MUX_16.taw.rdb
...\..\MUX_16.tis_db_list.ddb
...\..\MUX_16.tmw_info
...\..\MUX_16.vpr.ammdb
...\..\prev_cmp_MUX_16.qmsg
...\incremental_db\compiled_partitions\MUX_16.db_info
...\..............\...................\MUX_16.root_partition.map.kpt
...\..............\README
...\MUX_16.jdi
...\MUX_16.qpf
...\MUX_16.qsf
...\MUX_16.qws
...\MUX_16.sdc
...\MUX_16.v
...\MUX_16.v.bak
...\MUX_16_nativelink_simulation.rpt
...\output_files\MUX_16.asm.rpt
...\............\MUX_16.done
...\............\MUX_16.eda.rpt
...\............\MUX_16.fit.rpt
...\............\MUX_16.fit.smsg
...\............\MUX_16.fit.summary
...\............\MUX_16.flow.rpt
...\............\MUX_16.jdi
...\............\MUX_16.map.rpt
...\............\MUX_16.map.summary
...\............\MUX_16.pin
...\............\MUX_16.pof
...\............\MUX_16.sta.rpt
...\............\MUX_16.sta.summary
...\simulation\modelsim\modelsim.ini
...\..........\........\msim_transcript
...\..........\........\MUX_16.sft
...\..........\........\MUX_16.vo
...\..........\........\MUX_16.vt
...\..........\........\MUX_16.vt.bak
...\..........\........\MUX_16_modelsim.xrf
...\..........\........\MUX_16_run_msim_rtl_verilog.do
...\..........\........\MUX_16_run_msim_rtl_verilog.do.bak
...\..........\........\MUX_16_run_msim_rtl_verilog.do.bak1
...\..........\........\MUX_16_run_msim_rtl_verilog.do.bak2
...\..........\........\MUX_16_run_msim_rtl_verilog.do.bak3
...\..........\........\MUX_16_run_msim_rtl_verilog.do.bak4
...\..........\........\MUX_16_v.sdo
...\..........\........\rtl_work\@m@u@x_16\verilog.prw
...\..........\........\........\.........\verilog.psm
...\..........\........\........\.........\_primary.dat
...\..........\........\........\.........\_primary.dbs
...\..........\........\........\.........\_primary.vhd
...\..........\........\........\........._vlg_tst\verilog.prw
...\..........\........\........\.................\verilog.psm
...\..........\........\........\.................\_primary.dat
...\..........\........\........\.................\_primary.dbs
...\..........\........\........\.................\_primary.vhd
...\..........\........\........\_info
...\..........\........\........\_vmake

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