FPGA-based digital display, to see friends just getting started. .

EX3\db\LED_SEG7_2.asm.qmsg
...\..\LED_SEG7_2.asm.rdb
...\..\LED_SEG7_2.asm_labs.ddb
...\..\LED_SEG7_2.atom_map.rvd
...\..\LED_SEG7_2.cbx.xml
...\..\LED_SEG7_2.cmp.cdb
...\..\LED_SEG7_2.cmp.hdb
...\..\LED_SEG7_2.cmp.idb
...\..\LED_SEG7_2.cmp.kpt
...\..\LED_SEG7_2.cmp.logdb
...\..\LED_SEG7_2.cmp.rdb
...\..\LED_SEG7_2.cmp0.ddb
...\..\LED_SEG7_2.db_info
...\..\LED_SEG7_2.eda.qmsg
...\..\LED_SEG7_2.fit.qmsg
...\..\LED_SEG7_2.hier_info
...\..\LED_SEG7_2.hif
...\..\LED_SEG7_2.ipinfo
...\..\LED_SEG7_2.lpc.html
...\..\LED_SEG7_2.lpc.rdb
...\..\LED_SEG7_2.lpc.txt
...\..\LED_SEG7_2.map.cdb
...\..\LED_SEG7_2.map.hdb
...\..\LED_SEG7_2.map.logdb
...\..\LED_SEG7_2.map.qmsg
...\..\LED_SEG7_2.map.rdb
...\..\LED_SEG7_2.pplq.rdb
...\..\LED_SEG7_2.pre_map.cdb
...\..\LED_SEG7_2.pre_map.hdb
...\..\LED_SEG7_2.qns
...\..\LED_SEG7_2.root_partition.map.reg_db.cdb
...\..\LED_SEG7_2.routing.rdb
...\..\LED_SEG7_2.rpp.qmsg
...\..\LED_SEG7_2.rtlv.hdb
...\..\LED_SEG7_2.rtlv_sg.cdb
...\..\LED_SEG7_2.rtlv_sg_swap.cdb
...\..\LED_SEG7_2.sas
...\..\LED_SEG7_2.sgate.rvd
...\..\LED_SEG7_2.sgate_sm.rvd
...\..\LED_SEG7_2.sgdiff.cdb
...\..\LED_SEG7_2.sgdiff.hdb
...\..\LED_SEG7_2.sld_design_entry.sci
...\..\LED_SEG7_2.sld_design_entry_dsc.sci
...\..\LED_SEG7_2.smart_action.txt
...\..\LED_SEG7_2.sta.qmsg
...\..\LED_SEG7_2.sta.rdb
...\..\LED_SEG7_2.sta_cmp.5_slow.tdb
...\..\LED_SEG7_2.syn_hier_info
...\..\LED_SEG7_2.taw.rdb
...\..\LED_SEG7_2.tis_db_list.ddb
...\..\LED_SEG7_2.vpr.ammdb
...\..\logic_util_heursitic.dat
...\..\prev_cmp_LED_SEG7_2.qmsg
...\incremental_db\compiled_partitions\LED_SEG7_2.db_info
...\..............\...................\LED_SEG7_2.root_partition.map.kpt
...\..............\README
...\LED_SEG7_2.jdi
...\LED_SEG7_2.qpf
...\LED_SEG7_2.qsf
...\LED_SEG7_2.qws
...\LED_SEG7_2.sdc
...\LED_SEG7_2.v
...\LED_SEG7_2.v.bak
...\LED_SEG7_2_nativelink_simulation.rpt
...\output_files\LED_SEG7_2.asm.rpt
...\............\LED_SEG7_2.done
...\............\LED_SEG7_2.eda.rpt
...\............\LED_SEG7_2.fit.rpt
...\............\LED_SEG7_2.fit.smsg
...\............\LED_SEG7_2.fit.summary
...\............\LED_SEG7_2.flow.rpt
...\............\LED_SEG7_2.jdi
...\............\LED_SEG7_2.map.rpt
...\............\LED_SEG7_2.map.summary
...\............\LED_SEG7_2.pin
...\............\LED_SEG7_2.pof
...\............\LED_SEG7_2.sta.rpt
...\............\LED_SEG7_2.sta.summary
...\simulation\modelsim\LED_SEG7_2.sft
...\..........\........\LED_SEG7_2.vo
...\..........\........\LED_SEG7_2.vt
...\..........\........\LED_SEG7_2.vt.bak
...\..........\........\LED_SEG7_2_modelsim.xrf
...\..........\........\LED_SEG7_2_run_msim_rtl_verilog.do
...\..........\........\LED_SEG7_2_run_msim_rtl_verilog.do.bak
...\..........\........\LED_SEG7_2_run_msim_rtl_verilog.do.bak1
...\..........\........\LED_SEG7_2_run_msim_rtl_verilog.do.bak2
...\..........\........\LED_SEG7_2_run_msim_rtl_verilog.do.bak3
...\..........\........\LED_SEG7_2_run_msim_rtl_verilog.do.bak4
...\..........\........\LED_SEG7_2_v.sdo
...\..........\........\modelsim.ini
...\..........\........\msim_transcript
...\..........\........\rtl_work\@l@e@d_@s@e@g7_2\verilog.prw
...\..........\........\........\................\verilog.psm
...\..........\........\........\................\_primary.dat
...\..........\........\........\................\_primary.dbs
...\..........\........\........\................\_primary.vhd
...\..........\........\........\................_vlg_tst\verilog.prw
...\..........\........\........\........................\verilog.psm
...\..........\........\........\........................\_primary.dat

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