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data_recovery

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2013-07-07
  • Size : 150kb
  • Downloaded :0次
  • Author :liu****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
data clock decover xilinx example
Packet file list
(Preview for download)


verilog\design_files\data_recovery_virtex2.v
.......\............\data_recovery_virtex2_fast.v
.......\............\top_v2.v
.......\............\top_v2_fast.v
.......\simulation\tb_top_v2.v
.......\..........\tb_top_v2_fast.v
.......\..........\top_v2.do
.......\..........\top_v2_fast.do
.......\ucf\TOP_V2.UCF
.......\...\top_v2_fast.ucf
.......\xapp224.pdf
.......\design_files
.......\simulation
.......\ucf
verilog
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