This an fpga-based, using VHDL language, about 50M divider.

aaa\clk_1_gen.done
...\clk_1_gen.flow.rpt
...\clk_1_gen.map.rpt
...\clk_1_gen.map.summary
...\clk_1_gen.qpf
...\clk_1_gen.qsf
...\clk_1_gen.qws
...\clk_1_gen.vhd
...\clk_1_gen.vhd.bak
...\db\clk_1_gen.cbx.xml
...\..\clk_1_gen.cmp.rdb
...\..\clk_1_gen.cmp_merge.kpt
...\..\clk_1_gen.db_info
...\..\clk_1_gen.eco.cdb
...\..\clk_1_gen.hier_info
...\..\clk_1_gen.hif
...\..\clk_1_gen.lpc.html
...\..\clk_1_gen.lpc.rdb
...\..\clk_1_gen.lpc.txt
...\..\clk_1_gen.map.bpm
...\..\clk_1_gen.map.cdb
...\..\clk_1_gen.map.ecobp
...\..\clk_1_gen.map.hdb
...\..\clk_1_gen.map.kpt
...\..\clk_1_gen.map.logdb
...\..\clk_1_gen.map.qmsg
...\..\clk_1_gen.map_bb.cdb
...\..\clk_1_gen.map_bb.hdb
...\..\clk_1_gen.map_bb.logdb
...\..\clk_1_gen.pre_map.cdb
...\..\clk_1_gen.pre_map.hdb
...\..\clk_1_gen.rtlv.hdb
...\..\clk_1_gen.rtlv_sg.cdb
...\..\clk_1_gen.rtlv_sg_swap.cdb
...\..\clk_1_gen.sgdiff.cdb
...\..\clk_1_gen.sgdiff.hdb
...\..\clk_1_gen.sld_design_entry.sci
...\..\clk_1_gen.sld_design_entry_dsc.sci
...\..\clk_1_gen.syn_hier_info
...\..\clk_1_gen.tis_db_list.ddb
...\..\clk_1_gen.tmw_info
...\incremental_db\compiled_partitions\clk_1_gen.root_partition.map.atm
...\..............\...................\clk_1_gen.root_partition.map.dpi
...\..............\...................\clk_1_gen.root_partition.map.hdbx
...\..............\...................\clk_1_gen.root_partition.map.kpt
...\..............\README
...\..............\compiled_partitions
...\db
...\incremental_db
aaa

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