Introduction - If you have any usage issues, please Google them yourself
运用verilog语言实现的MIPS指令集，包括加、减、比较、与、异或等指令。运用五级流水线，设置IF，ID，EX，MEM、WB五个栈间计算模块。运用了forwarding和stop技术。可以使用modelsim验证。
Packet : MIPS.rar filelist
test.v
test.v.bak
vsim.wlf
WB.v
WB.v.bak
test/data.txt
test/data1.txt
test/LbLj1.txt
test/LbLj1_data.txt
test/LbLj1_result.txt
test/LbLj2.txt
test/LbLj2_data.txt
test/LbLj2_result.txt
test/MbMj1.txt
test/MbMj1_data.txt
test/MbMj1_result.txt
test/MbMj2.txt
test/MbMj2_data.txt
test/MbMj2_result.txt
test/NbNj1.txt
test/NbNj1_data.txt
test/NbNj1_result.txt
test/NbNj2.txt
test/NbNj2_data.txt
test/NbNj2_result.txt
test/result.txt
test/result1.txt
test/result1_jump.txt
work/@c@o@a_@t@o@p/verilog.asm
work/@c@o@a_@t@o@p/_primary.dat
work/@c@o@a_@t@o@p/_primary.dbs
work/@c@o@a_@t@o@p/_primary.vhd
work/@e@x/verilog.asm
work/@e@x/_primary.dat
work/@e@x/_primary.dbs
work/@e@x/_primary.vhd
work/@i@d/verilog.asm
work/@i@d/_primary.dat
work/@i@d/_primary.dbs
work/@i@d/_primary.vhd
work/@i@f/verilog.asm
work/@i@f/_primary.dat
work/@i@f/_primary.dbs
work/@i@f/_primary.vhd
work/@m@e@m/verilog.asm
work/@m@e@m/_primary.dat
work/@m@e@m/_primary.dbs
work/@m@e@m/_primary.vhd
work/@w@b/verilog.asm
work/@w@b/_primary.dat
work/@w@b/_primary.dbs
work/@w@b/_primary.vhd
work/test/verilog.asm
work/test/_primary.dat
work/test/_primary.dbs
work/test/_primary.vhd
work/_info
work/_temp/vlog28e5mv
work/_temp/vlog3hxd75
work/_temp/vlog3xv02f
work/_temp/vlog5bv23f
work/_temp/vlog5ny1sd
work/_temp/vlog9h23kx
work/_temp/vlog9xm9dn
work/_temp/vlogafx9ix
work/_temp/vlogdbir2c
work/_temp/vlogezt6vb
work/_temp/vlogfd2qkh
work/_temp/vlogihh9b2
work/_temp/vlogkz48d4
work/_temp/vlogm45z95
work/_temp/vlogm92hx4
work/_temp/vlogx7n6h0
coa.cr.mti
coa.mpf
COA_TOP.v
COA_TOP.v.bak
EX.v
EX.v.bak
ID.v
ID.v.bak
IF.v
IF.v.bak
MEM.v
MEM.v.bak
modelsim.ini
work/@c@o@a_@t@o@p
work/@e@x
work/@i@d
work/@i@f
work/@m@e@m
work/@w@b
work/test
work/_temp
test
work