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SignalTap-II

  • Category : VHDL-FPGA-Verilog
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  • Update : 2013-06-25
  • Size : 24.54mb
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  • Author :环***
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Introduction - If you have any usage issues, please Google them yourself
FPGA Application Development and Typical examples of code, typical examples 9 SignalTap II functional demo
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典型实例9 SignalTap II 功能演示\典型实例9 SignalTap II 功能演示\S3_WAVE\PROJ\cmp_state.ini
...............................\...............................\.......\....\COUNTER.bsf
...............................\...............................\.......\....\COUNTER.v
...............................\...............................\.......\....\COUNTER_bb.v
...............................\...............................\.......\....\COUNTER_wave0.jpg
...............................\...............................\.......\....\COUNTER_waveforms.html
...............................\...............................\.......\....\div.bsf
...............................\...............................\.......\....\div.v
...............................\...............................\.......\....\h.bsf
...............................\...............................\.......\....\h.v
...............................\...............................\.......\....\h_bb.v
...............................\...............................\.......\....\insystem.bmp
...............................\...............................\.......\....\PROJ.rar
...............................\...............................\.......\....\ROM.bsf
...............................\...............................\.......\....\ROM.v
...............................\...............................\.......\....\ROM_bb.v
...............................\...............................\.......\....\serv_req_info.txt
...............................\...............................\.......\....\signal-tap.bmp
...............................\...............................\.......\....\..mulation\modelsim\cyclone_atoms.v
...............................\...............................\.......\....\..........\........\vsim.wlf
...............................\...............................\.......\....\..........\........\wave.do
...............................\...............................\.......\....\..........\........\WAVE.vo
...............................\...............................\.......\....\..........\........\WAVE_modelsim.xrf
...............................\...............................\.......\....\..........\........\wave_test.cr.mti
...............................\...............................\.......\....\..........\........\wave_test.mpf
...............................\...............................\.......\....\..........\........\WAVE_TOP.V
...............................\...............................\.......\....\..........\........\WAVE_v.sdo
...............................\...............................\.......\....\..........\........\work\@c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e\verilog.asm
...............................\...............................\.......\....\..........\........\....\................................\_primary.dat
...............................\...............................\.......\....\..........\........\....\................................\_primary.vhd
...............................\...............................\.......\....\..........\........\....\.w@a@v@e\verilog.asm
...............................\...............................\.......\....\..........\........\....\........\_primary.dat
...............................\...............................\.......\....\..........\........\....\........\_primary.vhd
...............................\...............................\.......\....\..........\........\....\cyclone_and1\verilog.asm
...............................\...............................\.......\....\..........\........\....\............\_primary.dat
...............................\...............................\.......\....\..........\........\....\............\_primary.vhd
...............................\...............................\.......\....\..........\........\....\............6\verilog.asm
...............................\...............................\.......\....\..........\........\....\.............\_primary.dat
...............................\...............................\....
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